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T1 / E1 / J1 OCTAL FRAMER
IDT82V2108
PRELIMINARY
FEATURES
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Octal Framer supporting T1, E1 and J1 Formats Provides programmable system interface to support Mitel(R) STbus, AT&T(R) CHI and MVIP bus, supporting data rates of 1.544 / 2.048 / 8.192Mb/s; up to four links can be byte interleaved on one system bus without external logic Provides up to three internal floating HDLC controllers for each framer to support ISDN PRI and V5.X interface. Each HDLC contains 128-byte deep FIFOs in both the receive and transmit directions Provides jitter attenuation performance exceeding the requirements set by the associated standards for both Rx and Tx path Provides payload, line and digital loop-backs Provides a floating Pseudo Random Bit Sequence / repetitive pattern generator/detector, which can be assigned to any one of eight framers, the pattern may be inserted / detected in an unframed or Nx64K or Nx56K (T1 only) basis Provides signaling insertion / extraction for CCS / CAS and RBS signaling system Provides programmable codes insertion, data / sign inversion and digital milliwatt code insertion on a per channel / timeslot basis Supports automatic / manual alarming transmit and integration Provides performance monitor to counter CRC error, framing bit error, far end block CRC error (E1), out of frame event (T1/J1) and change of frame alignment event (T1/J1) Provides programmable In-band Loop-back Code transmitter/receiver, Bit Oriented Message generator / detector Supports polled or interrupt driven processing for all events Supports multiplexed or non-multiplexed address/data bus MPU interface for configuration, control and status monitoring JTAG boundary scan meets IEEE 1149.1 Low power 3.3V CMOS technology with 5V tolerant inputs Operating industrial temperature range: -40C to +85C Package available: 128 pin PQFP 144 pin PBGA
APPLICATIONS
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High density internet E1 or T1 / J1 interface for routers, multiplexers, switches and digital modems. Frame relay switches and access devices (FRADS) SONET / SDH add drop multiplexers Digital private branch exchanges (PBX) Channel service units (CSU) and data service units (DSU) Channel banks and multiplexers Digital access and cross-connect systems (DACS)
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STANDARDS
E1 MODE: ITU-T: G.704, G.706, G.732, G.802, G.737, G.738, G.739, G.742, G.823, G.964, G.965, I.431, O.151, O.152, O.153; ETSI: ETS 300 011, ETS 300 233, ETS 324-1, ETS 347-1, TBR 4, TBR 12, TBR 13; GO - MVIP T1/J1 MODE: ANSI: T1.107, T1.231, T1.403, T1.408; TR: TSY-000147, TSY-000191, NWT-000303, TSY-000312, TSY-000499; AT&T: TR 54016, TR 62411 TTC: JT-G 703, JT-G 704, JT-G706, JT-G 1431
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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(c) 2001 Integrated Device Technology, Inc.
JANUARY 2003
DSC-6039/3
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
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DESCRIPTION
The IDT82V2108 is a flexible feature-rich octal T1/E1/J1 Framer. Controlled by the software, the IDT82V2108 can be globally configured as an Octal E1 or T1/J1 Framer. When E1 or T1/J1 has been set globally, the operation mode of each of the eight framers can be configured independently. The configuration is performed through a parallel Multiplexed/Non-Multiplexed microprocessor interface. The IDT82V2108 realizes frame synchronization, frame generating, signaling extraction and insertion, alarm and test signals generation and detection in a single chip. It also integrates up to three HDLC receivers and HDLC transmitters for each of the eight framers. In E1 Mode, the receive path of each framer can be configured to frame to Basic Frame, CRC Multi-Frame and Signaling Multi-Frame. The framing can also be bypassed (unframed mode). It detects and indicates the event of out of Basic Frame Sync, out of CRC MultiFrame, out of Signaling Multi-Frame, the Remote Alarm Indication signal and the Remote Signaling Multi-Frame Alarm Indication signal. It also monitors the Red and AIS alarms. Basic Frame Alignment Signal errors, Far End Block Errors (FEBE) and CRC errors are counted. Up to three HDLC links are provided to extract the HDLC message on TS16, the Sa National bits and/or any arbitrary timeslot. An Elastic Store Buffer that optionally supports slip buffering and adaptation to backplane timing is provided. In E1 receive path, signaling debounce, signaling freezing, idle code substitution, digital milliwatt code insertion, trunk conditioning, data inversion and pattern generation or detection are also supported on a per-timeslot basis. In E1 mode, the transmit path of each framer can be configured to generate Basic Frame, CRC Multi-Frame and Signaling Multi-Frame. The framing can also be disabled (unframed mode). It can also transmit Remote Alarm Indication signal, the Remote Signaling Multi-Frame Alarm Indication signal, AIS signal and FEBE. Up to three HDLC links are provided to insert the HDLC message on TS16, the Sa National bits and/or any arbitrary timeslot. The signaling insertion, idle code substitution, data insertion, data inversion and test pattern generation or detection are also supported on a per-timeslot basis. In E1 mode, any four of the eight framers can be multiplexed or demultiplexed to or from one of the two 8.192M bit/s buses. In T1/J1 mode, the receive path of each framer can be configured to frame to Super Frame (SF) or Extended Super Frame (ESF) formats. The framing can also be bypassed (unframed mode). It detects and indicates the out of SF/ESF sync event, the Yellow, Red and AIS alarms. It also detects the presence of inband loopback codes, bit oriented message. Frame Alignment Signal errors, CRC-6 errors, out of SF/ESF events and Frame Alignment position changes are counted. Up to two HDLC links are provides to extract the HDLC message on the Fbit or any arbitrary channels in ESF mode. An Elastic Store Buffer that optionally supports controlled slip and adaptation to backplane timing is provided. In T1/J1 receive path, signaling debounce, signaling freezing, idle code substitution, digital milliwatt code insertion, idle code insertion, data inversion and pattern generation or detection are also supported on a per-channel basis. In T1/J1 mode, the transmit path of each framer can be configured to generates SF or ESF. The framing can also be disabled (unframed mode). It can also transmit Yellow signal and AIS signal. Inband loopback codes and bit oriented message can also be transmitted. Up to two HDLC links are provided to insert the HDLC message on the F-
bit or any arbitrary channels in ESF mode. The signaling insertion, idle code substitution, data insertion, data inversion and test pattern generation or detection are also supported on a per-channel basis. In T1/J1 mode, the data stream of 1.544M bit/s can be converted to/ from the data stream of 2.048M bit/s on the system side by software configuration. In addition, any four of the eight framers can be multiplexed or de-multiplexed to or from one of the two 8.192M bit/s buses.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
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FUNCTIONAL BLOCK DIAGRAM
One of the Eight Framers
TSCCKA TSCCKB/ MTSCCKB TSCFS/ MTSCFS MTSSIG[1:2] MTSD[1:2] TSFSn/ TSSIGn TSDn Transmit Clock Transmit System Interface
Transmit Payload Control
Frame Generator
Transmit Jitter Attenuator
LTCKn LTDn
Inband Bit-Oriented Loopback HDLC #3 Message Code Transmitter #2 (E1 Transmitter Generator #1 only) (T1/J1 only) (T1/J1 only) Payload Loopback PRBS Generator /Detector Bit-Oriented Message Receiver (T1/J1 only)
Digital Loopback
Inband Loopback Code Detector (T1/J1 only)
XCK
Alarm #3 HDLC Detector Receiver #1 #2 (E1 (T1/J1 only) only) MRSD[1:2] MRSSIG[1:2] MRSFS[1:2] RSCCK/ MRSCCK RSCFS/ MRSCFS RSDn RSCKn/ RSSIGn RSFSn Receive System Interface Receive Payload Control Receive CAS/RBS Buffer Elastic Store Buffer
Line Loopback
Frame Processor Receive Jitter Attenuator
LRCKn LRDn
Performance Monitor
Micro-Processor Interface
IEEE1149.1 JTAG
BIAS VDDIO VDDC GNDIO GNDC
A[10:0] RD WR CS ALE INT RST D[7:0]
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TRST TMS TDI TCLK TDO
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
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CONTENTS
1 PIN ASSIGNMENTS ............................................................................................................................................ 13
1.1 128 PIN PQFP PACKAGE (TOP VIEW) .................................................................................................................................................. 13 1.2 144 PIN PBGA PACKAGE (BOTTOM VIEW) .......................................................................................................................................... 14
2 PIN DESCRIPTION .............................................................................................................................................. 15 3 FUNCTIONAL DESCRIPTION .............................................................................................................................. 21
3.1 T1 / E1 / J1 MODE SELECTION ............................................................................................................................................................. 21 3.2 FRAME PROCESSOR (FRMP) ............................................................................................................................................................... 21 3.2.1 E1 Mode ......................................................................................................................................................................................... 21 3.2.2 T1/J1 Mode .................................................................................................................................................................................... 26 3.3 PERFORMANCE MONITOR (PMON) ..................................................................................................................................................... 28 3.3.1 E1 Mode ......................................................................................................................................................................................... 28 3.3.2 T1/J1 Mode .................................................................................................................................................................................... 28 3.4 ALARM DETECTOR (ALMD) - T1 / J1 ONLY .......................................................................................................................................... 28 3.5 HDLC RECEIVER (RHDLC) ................................................................................................................................................................... 29 3.5.1 E1 Mode ......................................................................................................................................................................................... 29 3.5.2 T1 / J1 Mode .................................................................................................................................................................................. 30 3.6 BIT-ORIENTED MESSAGE RECEIVER (RBOM) - T1 / J1 ONLY ............................................................................................................. 30 3.7 INBAND LOOPBACK CODE DETECTOR (IBCD) - T1 / J1 ONLY ........................................................................................................... 31 3.8 ELASTIC STORE BUFFER (ELSB) ........................................................................................................................................................ 31 3.8.1 E1 Mode ......................................................................................................................................................................................... 31 3.8.2 T1 / J1 Mode .................................................................................................................................................................................. 31 3.9 RECEIVE CAS/RBS BUFFER (RCRB) ................................................................................................................................................... 31 3.9.1 E1 Mode ......................................................................................................................................................................................... 31 3.9.2 T1 / J1 Mode .................................................................................................................................................................................. 33 3.10 RECEIVE PAYLOAD CONTROL (RPLC) .............................................................................................................................................. 33 3.10.1 E1 Mode ....................................................................................................................................................................................... 33 3.10.2 T1 / J1 Mode ................................................................................................................................................................................ 34 3.11 RECEIVE SYSTEM INTERFACE (RESI) ............................................................................................................................................... 35 3.11.1 E1 Mode ....................................................................................................................................................................................... 35 3.11.1.1 Receive Clock Slave Mode .................................................................................................................................................... 3.11.1.1.1 Receive Clock Slave RSCK Reference Mode ........................................................................................................ 3.11.1.1.2 Receive Clock Slave External Signaling Mode ...................................................................................................... 3.11.1.2 Receive Clock Master Mode ................................................................................................................................................... 3.11.1.2.1 Receive Clock Master Full E1 Mode ..................................................................................................................... 3.11.1.2.2 Receive Clock Master Fractional E1 (with F-bit) Mode ........................................................................................... 3.11.1.3 Receive Multiplexed Mode ..................................................................................................................................................... 36 36 38 39 39 41 41
3.11.1.4 Parity Check & Polarity Fix ..................................................................................................................................................... 43 3.11.1.5 Offset .................................................................................................................................................................................... 44 3.11.1.6 Output On RSDn/MRSD & RSSIGn/MRSSIG ......................................................................................................................... 44
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
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3.11.2 T1 / J1 Mode ................................................................................................................................................................................ 47 3.11.2.1 Receive Clock Slave Mode .................................................................................................................................................... 3.11.2.1.1 Receive Clock Slave RSCK Reference Mode ........................................................................................................ 3.11.2.1.2 Receive Clock Slave External Signaling Mode ...................................................................................................... 3.11.2.2 Receive Clock Master Mode ................................................................................................................................................... 3.11.2.2.1 Receive Clock Master Full T1/J1 Mode ................................................................................................................. 3.11.2.2.2 Receive Clock Master Fractional T1/J1 Mode ....................................................................................................... 3.11.2.3 Receive Multiplexed Mode ..................................................................................................................................................... 47 48 50 50 52 52 52
3.11.2.4 Parity Check .......................................................................................................................................................................... 53 3.11.2.5 Offset .................................................................................................................................................................................... 55 3.11.2.6 Output On RSDn/MRSD & RSSIGn/MRSSIG ......................................................................................................................... 55 3.12 PRBS GENERATOR / DETECT OR (PRGD) .......................................................................................................................................... 56 3.12.1 E1 Mode ....................................................................................................................................................................................... 56 3.12.2 T1 / J1 Mode ................................................................................................................................................................................ 57 3.13 TRANSMIT SYSTEM INTERFACE (TRSI) ............................................................................................................................................. 57 3.13.1 E1 Mode ....................................................................................................................................................................................... 57 3.13.1.1 Transmit Clock Slave Mode ................................................................................................................................................... 3.13.1.1.1 Transmit Clock Slave TSFS Enable Mode ........................................................................................................... 3.13.1.1.2 Transmit Clock Slave External Signaling Mode ................................................................................................... 3.13.1.2 Transmit Clock Master Mode .................................................................................................................................................. 58 58 60 61
3.13.1.3 Transmit Multiplexed Mode .................................................................................................................................................... 61 3.13.1.4 Parity Check .......................................................................................................................................................................... 63 3.13.1.5 Offset .................................................................................................................................................................................... 65 3.13.2 T1 / J1 Mode ................................................................................................................................................................................ 68 3.13.2.1 Transmit Clock Slave Mode ................................................................................................................................................... 3.13.2.1.1 Transmit Clock Slave TSFS Enable Mode ........................................................................................................... 3.13.2.1.2 Transmit Clock Slave External Signaling Mode ................................................................................................... 3.13.2.2 Transmit Clock Master Mode .................................................................................................................................................. 68 69 71 72
3.13.2.3 Transmit Multiplexed Mode .................................................................................................................................................... 72 3.13.2.4 Parity Check .......................................................................................................................................................................... 75 3.13.2.5 Offset .................................................................................................................................................................................... 75 3.14 TRANSMIT PAYLOAD CONTROL (TPLC) ............................................................................................................................................ 76 3.14.1 E1 Mode ....................................................................................................................................................................................... 76 3.14.2 T1 / J1 Mode ................................................................................................................................................................................ 76 3.15 FRAME GENERATOR (FRMG) ............................................................................................................................................................. 77 3.15.1 E1 Mode ....................................................................................................................................................................................... 77 3.15.2 T1 / J1 Mode ................................................................................................................................................................................ 78 3.16 HDLC TRANSMITTER (THDLC) ........................................................................................................................................................... 79 3.16.1 E1 Mode ....................................................................................................................................................................................... 79 3.16.2 T1 / J1 Mode ................................................................................................................................................................................ 79 3.17 BIT-ORIENTED MESSAGE TRANSMITTER (TBOM) - T1 / J1 ONLY .................................................................................................... 80 3.18 INBAND LOOPBACK CODE GENERATOR (IBCG) - T1 / J1 ONLY ...................................................................................................... 80
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
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3.19 JITTER ATTENUATOR (RJAT/TJAT) .................................................................................................................................................... 80 3.19.1 E1 Mode ...................................................................................................................................................................................... 80 3.19.2 T1 / J1 Mode ................................................................................................................................................................................ 83 3.20 TRANSMIT CLOCK .............................................................................................................................................................................. 85 3.20.1 E1 Mode ...................................................................................................................................................................................... 85 3.20.2 T1 / J1 Mode ................................................................................................................................................................................ 85 3.21 LINE INTERFACE ................................................................................................................................................................................ 85 3.21.1 E1 Mode ...................................................................................................................................................................................... 85 3.21.2 T1 / J1 Mode ................................................................................................................................................................................ 85 3.22 INTERRUPT SUMMARY ...................................................................................................................................................................... 86 3.22.1 E1 Mode ...................................................................................................................................................................................... 86 3.22.2 T1 / J1 Mode ................................................................................................................................................................................ 86 3.23 LOOPBACK MODE .............................................................................................................................................................................. 86 3.23.1 Line Loopback ............................................................................................................................................................................ 86 3.23.2 Digital Loopback ......................................................................................................................................................................... 86 3.23.3 Payload Loopback ...................................................................................................................................................................... 86 3.24 CLOCK MONITOR ............................................................................................................................................................................... 86
4 OPERATION ....................................................................................................................................................... 90
4.1 E1 MODE ............................................................................................................................................................................................... 90 4.1.1 Default Setting .............................................................................................................................................................................. 90 4.1.2 Various Operation Modes Configuration ...................................................................................................................................... 90 4.1.3 Operation Example ....................................................................................................................................................................... 95 4.1.3.1 Using The HDLC Receiver ....................................................................................................................................................... 95 4.1.3.2 Using The HDLC Transmitter ................................................................................................................................................... 95 4.1.3.3 Using The PRBS Generator / Detector ..................................................................................................................................... 99 4.1.3.4 Using Payload Control and Receive CAS/RBS Buffer .............................................................................................................. 104 4.1.3.5 Using TJAT / Timing Option .................................................................................................................................................... 104 4.2 T1/J1 MODE ......................................................................................................................................................................................... 105 4.2.1 Default Setting ............................................................................................................................................................................. 105 4.2.2 OPERATION IN J1 MODE ............................................................................................................................................................. 105 4.2.3 Various Operation Modes Configuration ..................................................................................................................................... 105 4.2.4 Operation Example ...................................................................................................................................................................... 110 4.2.4.1 Using The HDLC Receiver ...................................................................................................................................................... 110 4.2.4.2 Using The HDLC Transmitter .................................................................................................................................................. 112 4.2.4.3 Using The PRBS Generator / Detector .................................................................................................................................... 114 4.2.4.4 Using Payload Control and Receive CAS/RBS Buffer .............................................................................................................. 118 4.2.4.5 Using TJAT / Timing Option .................................................................................................................................................... 118
5 PROGRAMMING INFORMATION ....................................................................................................................... 119
5.1 REGISTER MAP ................................................................................................................................................................................... 119
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
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5.1.1 E1 Mode Register Map ................................................................................................................................................................ 120 5.1.2 T1 / J1 Mode Register Map ......................................................................................................................................................... 123 5.2 REGISTER DESCRIPTION .................................................................................................................................................................. 126 5.2.1 E1 Mode ...................................................................................................................................................................................... 126 5.2.2 T1 / J1 Mode ................................................................................................................................................................................ 198
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ................................................................................................... 259
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) ............................................................................................................... 261 6.2 JTAG DATA REGISTER ....................................................................................................................................................................... 261 6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 261 6.2.2 Bypass Register (BYR) ............................................................................................................................................................... 261 6.2.3 Boundary Scan Register (BSR) .................................................................................................................................................. 261 6.3 TEST ACCESS PORT CONTROLLER ................................................................................................................................................. 261
7 PHYSICAL AND ELECTRICAL SPECIFICATIONS .............................................................................................. 265
7.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................................................ 265 7.2 OPERATING CONDITIONS .................................................................................................................................................................. 265 7.3 D.C. CHARACTERISTICS .................................................................................................................................................................... 265 7.4 CLOCK RESET TIMING ....................................................................................................................................................................... 266 7.4.1 Clock Parameters E1 Configuration ........................................................................................................................................... 266 7.4.2 Clock Parameters T1/J1 Configuration ...................................................................................................................................... 266 7.5 MICROPROCESSOR READ ACCESS TIMING .................................................................................................................................... 267 7.6 MICROPROCESSOR WRITE ACCESS TIMING ................................................................................................................................... 268 7.7 I/O TIMING CHARACTERISTICS ......................................................................................................................................................... 269 7.7.1 Transmit System Interface Timing .............................................................................................................................................. 269 7.7.2 Receive System Interface Timing ............................................................................................................................................... 270 7.7.3 Receive & Transmit Line Timing ................................................................................................................................................. 271 7.7.3.1 Receive Line Interface Timing ............................................................................................................................................... 271 7.7.3.2 Transmit Line Interface Timing ............................................................................................................................................... 271
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
LIST OF FIGURES
Figure - 1. E1 Frame Searching Process ........................................................................................................................................................... 22 Figure - 2. Basic Frame Searching Process ...................................................................................................................................................... 23 Figure - 3. HDLC Packet .................................................................................................................................................................................... 29 Figure - 4. TS16 Arrangement in Signaling Multi-Frame ................................................................................................................................... 32 Figure - 5. Signaling Output in E1 Mode ........................................................................................................................................................... 32 Figure - 6. Signaling Output in T1 / J1 Mode ..................................................................................................................................................... 32 Figure - 7. Receive Clock Slave RSCK Reference Mode ................................................................................................................................... 36 Figure - 8. E1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 1 ............................................................................ 37 Figure - 9. E1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 2 ............................................................................ 37 Figure - 10. Receive Clock Slave External Signaling Mode .............................................................................................................................. 38 Figure - 11. E1 Receive Clock Slave External Signaling Mode - Functional Timing Example 1 ........................................................................ 38 Figure - 12. E1 Receive Clock Slave External Signaling Mode - Functional Timing Example 2 ....................................................................... 39 Figure - 13. Receive Clock Master Full E1 or T1/J1 Mode ................................................................................................................................. 40 Figure - 14. E1 Receive Clock Master Full E1 Mode - Functional Timing Example ........................................................................................... 40 Figure - 15. Receive Clock Master Fractional E1 or T1/J1 Mode ....................................................................................................................... 41 Figure - 16. E1 Receive Clock Master Fractional E1 Mode - Functional Timing Example ................................................................................ 42 Figure - 17. Receive Multiplexed Mode ............................................................................................................................................................. 43 Figure - 18. E1 Receive Multiplexed Mode - Functional Timing Example 1 ...................................................................................................... 43 Figure - 19. E1 Receive Multiplexed Mode - Functional Timing Example 2 ...................................................................................................... 44 Figure - 20. Receive Bit Offset - Between RSCFS & RSDn ................................................................................................................................ 46 Figure - 21. Receive Bit Offset - Between RSFSn & RSDn ................................................................................................................................ 46 Figure - 22. T1/J1 To E1 Format Conversion ..................................................................................................................................................... 48 Figure - 23. T1/J1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 1 ..................................................................... 48 Figure - 24. T1/J1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 2 ..................................................................... 49 Figure - 25. T1/J1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 3 ..................................................................... 49 Figure - 26. T1/J1 Receive Clock Slave External Signaling Mode - Functional Timing Example 1 ................................................................... 50 Figure - 27. T1/J1 Receive Clock Slave External Signaling Mode - Functional Timing Example 2 ................................................................... 51 Figure - 28. T1/J1 Receive Clock Slave External Signaling Mode - Functional Timing Example 3 ................................................................... 51 Figure - 29. T1/J1 Receive Clock Master Full T1/J1 Mode - Functional Timing Example .................................................................................. 52 Figure - 30. T1/J1 Receive Clock Master Fractional T1/J1 Mode - Functional Timing Example ....................................................................... 53 Figure - 31. T1/J1 Receive Multiplexed Mode - Functional Timing Example 1 .................................................................................................. 54 Figure - 32. T1/J1 Receive Multiplexed Mode - Functional Timing Example 2 .................................................................................................. 54 Figure - 33. Receive Bit Offset in T1/J1 Mode ................................................................................................................................................... 55 Figure - 34. PRBS Pattern Generator ................................................................................................................................................................ 56 Figure - 35. Transmit Clock Slave TSFS Enable Mode ...................................................................................................................................... 58 Figure - 36. E1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 1 ............................................................................... 59 Figure - 37. E1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 2 ............................................................................... 59 Figure - 38. Transmit Clock Slave External Signaling Mode ............................................................................................................................. 60
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Figure - 39. E1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 1 ...................................................................... 60 Figure - 40. E1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2 ...................................................................... 61 Figure - 41. Transmit Clock Master Mode .......................................................................................................................................................... 61 Figure - 42. E1 Transmit Clock Master Mode - Functional Timing Example ..................................................................................................... 62 Figure - 43. Transmit Multiplexed Mode ............................................................................................................................................................ 63 Figure - 44. E1 Transmit Multiplexed Mode - Functional Timing Example 1 ..................................................................................................... 64 Figure - 45. E1 Transmit Multiplexed Mode - Functional Timing Example 2 ..................................................................................................... 64 Figure - 46. Transmit Bit Offset in E1 Mode - 1 ................................................................................................................................................. 65 Figure - 47. Transmit Bit Offset in E1 Mode - 2 ................................................................................................................................................. 66 Figure - 48. Transmit Bit Offset in E1 Mode - 3 ................................................................................................................................................. 66 Figure - 49. Transmit Bit Offset in E1 Mode - 4 ................................................................................................................................................. 67 Figure - 50. Transmit Bit Offset in E1 Mode - 5 ................................................................................................................................................. 67 Figure - 51. E1 To T1/J1 Format Conversion ..................................................................................................................................................... 69 Figure - 52. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 1 .......................................................................... 69 Figure - 53. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 2 .......................................................................... 70 Figure - 54. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 3 .......................................................................... 70 Figure - 55. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 1 ................................................................. 71 Figure - 56. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2 ................................................................. 71 Figure - 57. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 3 ................................................................. 72 Figure - 58. T1/J1 Transmit Clock Master Mode - Functional Timing Example ................................................................................................. 73 Figure - 59. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 1 ................................................................................................ 74 Figure - 60. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 2 ................................................................................................ 74 Figure - 61. Transmit Bit Offset in T1/J1 Mode - 1 ............................................................................................................................................. 75 Figure - 62. Transmit Bit Offset in T1/J1 Mode - 2 ............................................................................................................................................. 75 Figure - 63. E1 Mode Jitter Tolerance (N1 = N2 = 2fH) ....................................................................................................................................... 82 Figure - 64. E1 Mode Jitter Transfer (N1 = N2 = 2fH) ......................................................................................................................................... 82 Figure - 65. T1/J1 Mode Jitter Tolerance (N1 = N2 = 2fH) .................................................................................................................................. 84 Figure - 66. T1/J1 Mode Jitter Transfer (N1 = N2 = 2fH) .................................................................................................................................... 84 Figure - 67. Transmit Clock Select .................................................................................................................................................................... 85 Figure - 68. Line Loopback ................................................................................................................................................................................ 87 Figure - 69. Digital Loopback ............................................................................................................................................................................ 88 Figure - 70. Payload Loopback .......................................................................................................................................................................... 89 Figure - 71. Interrupt Service in E1 Mode HDLC Receiver ................................................................................................................................ 96 Figure - 72. Writing Data to E1 Mode THDLC FIFO ............................................................................................................................................ 97 Figure - 73. Interrupt Service in E1 Mode HDLC Transmitter ............................................................................................................................ 98 Figure - 74. Polling Mode in E1 Mode HDLC Transmitter .................................................................................................................................. 99 Figure - 75. Writing Sequence of Indirect Register in E1 Mode ...................................................................................................................... 104 Figure - 76. Reading Sequence of Indirect Register in E1 Mode .................................................................................................................... 104 Figure - 77. Interrupt Service in T1/J1 Mode HDLC Receiver ........................................................................................................................... 111 Figure - 78. Writing Data to T1/J1 Mode THDLC FIFO ...................................................................................................................................... 112
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Figure - 79. Interrupt Service in T1/J1 Mode HDLC Transmitter ...................................................................................................................... 113 Figure - 80. Polling Mode in T1/J1 Mode HDLC Transmitter ............................................................................................................................ 114 Figure - 81. Writing Sequence of Indirect Register in T1/J1 Mode ................................................................................................................... 118 Figure - 82. Reading Sequence of Indirect Register in T1/J1 Mode ................................................................................................................. 118 Figure - 83. JTAG Architecture ........................................................................................................................................................................ 259 Figure - 84. JTAG State Diagram ..................................................................................................................................................................... 264 Figure - 85. Read Access Timing ..................................................................................................................................................................... 267 Figure - 86. Write Access Timing ..................................................................................................................................................................... 268 Figure - 87. Transmit Interface Timing (Transmit System Common Clock #B) ............................................................................................... 269 Figure - 88. Transmit Interface Timing (Line Transmit Clock) ......................................................................................................................... 269 Figure - 89. Receive Interface Timing (Receive System Common Clock) ...................................................................................................... 270 Figure - 90. Receive Interface Timing (Receive System Clock) ...................................................................................................................... 270 Figure - 91. Receive Line Interface Timing ..................................................................................................................................................... 271 Figure - 92. Transmit Line Interface Timing .................................................................................................................................................... 271
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
LIST OF TABLES
Table - 1. The Structure Of TS0 ......................................................................................................................................................................... 23 Table - 2. Interrupt Sources In The E1 Frame Processor .................................................................................................................................. 25 Table - 3. The Structure Of SF Format ............................................................................................................................................................... 26 Table - 4. The Structure Of ESF Format ............................................................................................................................................................ 27 Table - 5. Interrupt Sources In The T1 / J1 Frame Processor ............................................................................................................................ 27 Table - 6. Basic Frame Alignment Pattern Error Counter .................................................................................................................................. 28 Table - 7. Alarm Summary in ALMD ................................................................................................................................................................... 29 Table - 8. A-Law Digital Milliwatt Pattern ........................................................................................................................................................... 34 Table - 9. u-Law Digital Milliwatt Pattern ........................................................................................................................................................... 34 Table - 10. E1 Mode Receive System Interface in Different Operation Modes .................................................................................................. 35 Table - 11. Operation Mode Selection in E1 Receive Path ................................................................................................................................ 35 Table - 12. Active Edge Selection of RSCCK (in E1 Receive Clock Slave RSCK Reference Mode) .................................................................. 36 Table - 13. Active Edge Selection of RSCCK (in E1 Receive Clock Slave External Signaling Mode) ............................................................... 38 Table - 14. Active Edge Selection of RSCK (in E1 Receive Clock Master Mode) .............................................................................................. 39 Table - 15. Active Edge Selection of MRSCCK (in E1 Receive Multiplexed Mode) ........................................................................................... 41 Table - 16. Offset in Different Operation Modes ................................................................................................................................................ 45 Table - 17. Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 0) .................................................................................................. 45 Table - 18. Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 1) .................................................................................................. 45 Table - 19. Bit Offset Between RSFSn and RSDn When the BRXSMFP and the ALTIFP (b2, b0, E1-011H) are Both Set To Logical 1 ............. 45 Table - 20. T1/J1 Mode Receive System Interface in Different Operation Modes ............................................................................................. 47 Table - 21. Operation Mode Selection in T1/J1 Receive Path ........................................................................................................................... 47 Table - 22. Active Edge Selection of RSCCK (in T1/J1 Receive Clock Slave RSCK Reference Mode) ............................................................. 48 Table - 23. Active Edge Selection of RSCCK (in T1/J1 Receive Clock Slave External Signaling Mode) ........................................................... 50 Table - 24. Active Edge Selection of MRSCCK (in T1/J1 Receive Multiplexed Mode) ....................................................................................... 52 Table - 25. Receive System Interface Bit Offset ................................................................................................................................................ 55 Table - 26. E1 Mode Transmit System Interface in Different Operation Modes ................................................................................................ 58 Table - 27. Operation Mode Selection in E1 Transmit Path ............................................................................................................................... 58 Table - 28. Active Edge Selection of TSCCKB (in E1 Transmit Clock Slave TSFS Enable Mode) ..................................................................... 60 Table - 29. Active Edge Selection of TSCCKB (in E1 Transmit Clock Slave External Signaling Mode) ............................................................ 60 Table - 30. Active Edge Selection of MTSCCKB (in E1 Transmit Multiplexed Mode) ........................................................................................ 63 Table - 31. Transmit System Interface Bit Offset (CHI [b3, E1-01CH] = 1, CMS [b2, E1-018H] = 0) ................................................................... 65 Table - 32. Transmit System Interface Bit Offset (CHI [b3, E1-01CH] = 1, CMS [b2, E1-018H] = 1) ................................................................... 65 Table - 33. T1/J1 Mode Transmit System Interface in Different Operation Modes ............................................................................................ 68 Table - 34. Operation Mode Selection in T1/J1 Transmit Path .......................................................................................................................... 68 Table - 35. Active Edge Selection of TSCCKB (in T1/J1 Transmit Clock Slave TSFS Enable Mode) ................................................................ 69 Table - 36. Remote Alarm Indication .................................................................................................................................................................. 77 Table - 37. Content in International Bits (when the INDIS [b1, E1-040H] is logic 0) .......................................................................................... 78 Table - 38. Interrupt Summary ........................................................................................................................................................................... 78
11
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 39. Default Setting in Receive Path ....................................................................................................................................................... 90 Table - 40. Default Setting in Transmit Path ...................................................................................................................................................... 90 Table - 41. Various Operation Modes in Receive Path for Reference ............................................................................................................... 91 Table - 42. Various Operation Modes in Transmit Path for Reference .............................................................................................................. 93 Table - 43. Example for Using HDLC Receiver .................................................................................................................................................. 95 Table - 44. Example for Using HDLC Transmitter .............................................................................................................................................. 97 Table - 45. Test Pattern .................................................................................................................................................................................... 100 Table - 46. The Setting of PRGD ...................................................................................................................................................................... 101 Table - 47. Initializtion of TPLC ........................................................................................................................................................................ 101 Table - 48. Initializtion of RPLC ....................................................................................................................................................................... 103 Table - 49. Error Insertion ................................................................................................................................................................................ 103 Table - 50. Default Setting in Receive Path ..................................................................................................................................................... 105 Table - 51. Default Setting in Transmit Path .................................................................................................................................................... 105 Table - 52. Various Operation Modes in Receive Path for Reference ............................................................................................................. 106 Table - 53. Various Operation Modes in Transmit Path for Reference ............................................................................................................ 108 Table - 54 . Example for Using HDLC Receiver ................................................................................................................................................ 110 Table - 55. Example for Using HDLC Transmitter ............................................................................................................................................. 112 Table - 56. Test Pattern ..................................................................................................................................................................................... 115 Table - 57. The Setting of PRGD ....................................................................................................................................................................... 116 Table - 58. Initializtion of TPLC ......................................................................................................................................................................... 116 Table - 59. Initializtion of RPLC ........................................................................................................................................................................ 117 Table - 60. Error Insertion ................................................................................................................................................................................. 118 Table - 61. T1/E1 Mode Selection Register ....................................................................................................................................................... 119 Table - 62a. E1 Mode Register Map - Direct Register ...................................................................................................................................... 120 Table - 62b. E1 Mode Register Map - Indirect Register ................................................................................................................................... 123 Table - 63a. T1/J1 Mode Register Map - Direct Register .................................................................................................................................. 123 Table - 63b. T1/J1 Mode Register Map - Indirect Register ............................................................................................................................... 125 Table - 64. IR Code ........................................................................................................................................................................................... 260 Table - 65. IDR .................................................................................................................................................................................................. 261 Table - 66. Boundary Scan Sequence and the I/O Pad Cell Type .................................................................................................................... 261 Table - 67. TAP Controller State Description ................................................................................................................................................... 263
12
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
1
1.1
PIN ASSIGNMENTS
128 PIN PQFP PACKAGE (TOP VIEW)
TMS TDI TCK TRST TDO TSCCKA TSCCKB/MTSCCKB TSCFS/MTSCFS RSCCK/MRSCCK RSCFS/MRSCFS GNDC[4] XCK VDDC[4] TSD[1]/MTSD[1] TSFS[1]/TSSIG[1]/MTSSIG[1] TSD[2]/MTSD[2] TSFS[2]/TSSIG[2]/MTSSIG[2] TSD[3] TSFS[3]/TSSIG[3] TSD[4] TESTSE VDDIO[3] TSFS[4]/TSSIG[4] TSD[5] TSFS[5]/TSSIG[5] TSD[6] 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
LRD[1] LRCK[1] LRD[2] LRCK[2] LRD[3] LRCK[3] LRD[4] LRCK[4] LTD[1] LTCK[1] LTD[2] LTCK[2] LTD[3] LTCK[3] LTD[4] LTCK[4] BIAS VDDIO[0] GNDIO[0] VDDC[0] GNDC[0] LTD[5] LTCK[5] LTD[6] LTCK[6] LTD[7] LTCK[7] LTD[8] LTCK[8] GNDIO[3] LRD[5] LRCK[5] LRD[6] LRCK[6] LRD[7] LRCK[7] LRD[8] LRCK[8]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
TSFS[6]/TSSIG[6] TSD[7] TSFS[7]/TSSIG[7] TSD[8] TSFS[8]/TSSIG[8] RSD[1]/MRSD[1] RSCK[1]/RSSIG[1]/MRSSIG[1] RSFS[1]/MRSFS[1] RSD[2]/MRSD[2] GNDC[3] VDDC[3] RSCK[2]/RSSIG[2]/MRSSIG[2] RSFS[2]/MRSFS[2] RSD[3] RSCK[3]/RSSIG[3] RSFS[3] GNDC[2] VDDC[2] RSD[4] RSCK[4]/RSSIG[4] RSFS[4] RSD[5] RSCK[5]/RSSIG[5] RSFS[5] RSD[6] RSCK[6]/RSSIG[6] RSFS[6] GNDIO[2] VDDIO[2] RSD[7] RSCK[7]/RSSIG[7] RSFS[7] RSD[8] RSCK[8]/RSSIG[8] RSFS[8] RD WR CS
RST INT D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] VDDIO[1 ] GNDIO[ 1] VDDC[1] GNDC[1] ALE A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]
13
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
IDT82V2108
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
1.2
144 PIN PBGA PACKAGE (BOTTOM VIEW)
12 11 10
TSFS[4]/ TSSIG[4]
9
8
7
TSFS[1]/ TSSIG[1]/ MTSSIG[1] TSD[1]/ MTSD[1]
6
5
RSCCK/ MRSCCK
4
3
2
1
A
TSD[7]
TSD[6]
GNDC[4]
TSD[3]
VDDC[3]
TSCCKA
TCK
LRD[1]
LRD[3]
A
B
RSD[1]/ MRSD[1]
TSD[8]
TSFS[6]/ TSSIG[6]
TSD[5]
TSFS[2]/ TSSIG[2]/ MTSSIG[2]
XCK
RSCFS/ MRSCFS
TSCCKB/ MTSCCKB
TMS
LRD[2]
LRD[4]
B
C
RSD[2]/ MRSD[2] RSCK[2]/ RSSIG[2]/ MRSSIG[2] RSCK[3]/ RSSIG[3]
RSCK[1]/ RSSIG[1]/ MRSSIG[1] RSFS[2]/ MRSFS[2]
TSFS[8]/ TSSIG[8]
TSFS[7]/ TSSIG[7]
VDDC[4]
TSFS[3]/ TSSIG[3]
GNDC[3]
TSCFS/ MTSCFS
TDO
LRCK[1]
LRCK[3]
LTCK[1]
C
D
VDDIO[3]
RSFS[1]/ MRSFS[1]
TSFS[5]/ TSSIG[5]
TSD[4]
TSD[2]/ MTSD[2]
TRST
TDI
LRCK[2]
LTD[1]
LTCK[2]
D
E
RSFS[3]
RSD[3]
GNDIO[3]
VDDC[5]
VDDC[6]
VDDC[7]
VDDC[8]
LRCK[4]
LTD[2]
LTCK[4]
LTD[4]
E
F
RSD[4]
VDDC[2]
GNDC[2]
RSD[5]
VDDC[9]
VDDC[10]
VDDC[11]
VDDC[12]
LTD[3]
LTCK[3]
GNDIO[0]
VDDIO[0]
F
G
RSFS[4]
RSCK[4]/ RSSIG[4]
RSD[6]
RSCK[6]/ RSSIG[6]
GNDC[5]
GNDC[6]
GNDC[7]
GNDC[8]
BIAS
LTD[5]
GNDC[0]
VDDC[0]
G
H
RSFS[5]
RSCK[5]/ RSSIG[5]
TESTSE
RSCK[7]/ RSSIG[7]
GNDC[9]
GNDC[10]
GNDC[11]
GNDC[12]
LTCK[8]
LTCK[6]
LTCK[5]
LTD[6]
H
J
RSFS[6]
RSD[7]
RSFS[8]
A[9]
A[7]
VDDIO[1]
D[4]
INT
LRD[5]
LTD[8]
LTD[7]
LTCK[7]
J
K
VDDIO[2]
RSD[8]
WR
A[6]
A[3]
A[0]
D[5]
D[2]
LRCK[7]
LRCK[6]
LRCK[5]
GNDIO[1]
K
L
RSFS[7]
RD
A[10]
A[4]
A[1]
ALE
VDDC[1]
D[7]
D[0]
LRCK[8]
LRD[7]
LRD[6]
L
M
RSCK[8]/ RSSIG[8]
CS
A[8]
A[5]
A[2]
GNDC[1]
GNDIO[2]
D[6]
D[3]
D[1]
RST
LRD[8]
M
12
11
10
9
8
7
6
5
4
3
2
1
14
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
2
PIN DESCRIPTION
Name LRD[1] LRD[2] LRD[3] LRD[4] LRD[5] LRD[6] LRD[7] LRD[8] LRCK[1] LRCK[2] LRCK[3] LRCK[4] LRCK[5] LRCK[6] LRCK[7] LRCK[8] RSCK[1]/RSSIG[1]/ MRSSIG[1] RSCK[2]/RSSIG[2]/ MRSSIG[2] RSCK[3]/RSSIG[3] RSCK[4]/RSSIG[4] RSCK[5]/RSSIG[5] RSCK[6]/RSSIG[6] RSCK[7]/RSSIG[7] RSCK[8]/RSSIG[8] Type Input Pin No. PQFP PBGA 1 3 5 7 31 33 35 37 2 4 6 8 32 34 36 38 96 91 88 83 80 77 72 69 A2 B2 A1 B1 J4 L1 L2 M1 C3 D3 C2 E4 K2 K3 K4 L3 C11 D12 E12 G11 H11 G9 H9 M12 Description Line and System Interface LRD[1:8]: Line Receive Data for Framer 1 ~ 8 These pins receive the data stream from line interface units or from a higher demultiplex interface. Data on these pins are sampled on the active edge of the corresponding LRCKn.
Input
LRCK[1:8]: Line Receive Clock for Framer 1 ~ 8 These pins receive externally recovered line clock (2.048 or 1.544 MHz). The clock is used to sample the data on the corresponding LRDn.
Output
RSCK[1:8]: Receive Side System Clock for Framer 1 ~ 8 In Receive Clock Master Full E1 or T1/J1 mode, the clock is a smoothed version of the corresponding 2.048 or 1.544 MHz Line Receive Clock (LRCK). The RSCKn is pulsed for each bit in the 256-bit or 193-bit frame. The corresponding RSFSn and RSDn pins are updated on the active edge of the RSCKn. In Receive Clock Master Nx64K mode, the clock is a gapped version of the associated smoothed LRCKn. The pulse number of the RSCKn in each frame is controllable from 0 to 255 or from 0 to 192 on a per-timeslot/channel basis. The corresponding RSFSn and RSDn pins are updated on the active edge of the RSCKn. In Receive Clock Slave RSCK Reference mode, the RSCKn can be selected to be either a 2.048/1.544 MHz jitter attenuated version of the corresponding LRCKn or an 8KHz clock divided down from the smoothed line clock LRCKn. RSSIG[1:8]: Receive Side System Signaling for Framer 1 ~ 8 In Receive Clock Slave External Signaling mode, the extracted signaling is output on these pins. The signal on these pins is timeslot/channel-aligned with the data output on the corresponding RSDn pin and is updated on the active edge of the RSCCK. The extracted signaling is located in the lower nibble (b5 ~ b8). In E1 mode, the extracted signaling repeats during the entire Signaling Multi-Frame for the same timeslot. In T1/J1 mode, the extracted signaling repeats during the entire SF/ESF for the same channel. MRSSIG[1:2]: Multiplexed Receive Side System Signaling When the multiplexed bus structure is configured, the extracted signaling data from the selected framers are multiplexed on these pins using a byte-interleaved multiplexing scheme. The data on the MRSSIG[1:2] are updated on the active edge of the MRSCCK. RSD[1:8]: Receive Side System Data for Framer 1 ~ 8 The processed data stream is output on these pins. In Receive Clock Master mode, the RSDn is updated on the active edge of the corresponding RSCKn. In Receive Clock Slave mode, the RSDn is updated on the active edge of the RSCCK. MRSD[1:2]: Multiplexed Receive Side System Data When the multiplexed bus structure is configured, the processed data stream from the selected framers is multiplexed on these pins using the byte-interleaved multiplexing scheme. The data on the MRSD[1:2] are updated on the active edge of the MRSCCK.
RSD[1]/MRSD[1] RSD[2]/MRSD[2] RSD[3] RSD[4] RSD[5] RSD[6] RSD[7] RSD[8]
Output
97 94 89 84 81 78 73 70
B12 C12 E10 F12 F9 G10 J11 K11
15
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name RSFS[1]/MRSFS[1] RSFS[2]/MRSFS[2] RSFS[3] RSFS[4] RSFS[5] RSFS[6] RSFS[7] RSFS[8] Type Output Pin No. PQFP PBGA D9 95 D11 90 E11 87 G12 82 H12 79 J12 76 L12 71 J10 68 Description RSFS[1:8]: Receive Side System Frame Pulse for Framer 1 ~ 8 In E1 mode, RSFSn can be configured to indicate the beginning of Basic Frame, or CRC Multi-Frame or/and Signaling Multi-Frame for data stream on RSDn. When configured for the Basic Frame, RSFSn will pulse high/low during the first bit of each Basic Frame. When configured for CRC Multi-Frame, RSFSn will pulse during the first bit of the first frame of the CRC Multi-Frame. When configured for the Signaling MultiFrame, RSFSn will pulse during the first bit of the first frame of the Signaling MultiFrame. When configured to indicate both Signaling and CRC Multi-Frame, RSFSn will go high/low on the first bit of the first frame of the Signaling Multi-Frame and go the opposite after the first bit of the first frame of the CRC Multi-Frame. In T1/J1 mode, RSFSn can be configured to indicate each F-bit, or the first F-bit of every 12-frame SF / every 24-frame ESF. RSFSn pulses during the above F-bit. In both E1 and T1/J1 mode, when Receive Clock Master mode is active, the RSFSn is updated on the active edge of the corresponding RSCKn. When Receive Clock Slave mode is active, the RSFSn is updated on the active edge of the RSCCK. MRSFS[1:2]: Multiplexed Receive Side System Frame Pulse When the multiplexed bus structure is configured, the signals on these pins indicate the beginning of a multiplexed frame. The MRSFS[1:2] are updated on the active edge of the MRSCCK. RSCCK: Receive Side System Common Clock RSCCK is used only in Receive Clock Slave mode. In E1 mode, it is a 2.048 or 4.096 MHz clock. In T1 mode, it is a 1.544 or 2.048 or 4.096 MHz clock. In Receive Clock Slave RSCK Reference mode, the RSDn and the RSFSn are updated and the RSCFS is sampled on the active edge of the RSCCK. In Receive Clock Slave External Signaling mode, the RSDn, the RSFSn and the RSSIGn are updated and the RSCFS is sampled on the active edge of the RSCCK. MRSCCK: Multiplexed Receive Side System Common Clock When the multiplexed bus structure is configured, MRSCCK is an 8.192 or 16.384 MHz clock for the receive system multiplexed bus. The MRSCFS is sampled and the MRSD[1:2], the MRSFS[1:2] and the MRSSIG[1:2] are updated on the active edge of the MRSCCK. RSCFS: Receive Side System Common Frame Pulse In Receive Clock Slave mode, RSCFS can be selected as a frame alignment reference. It is asserted on the request of each Basic Frame or each Multi-Frame in E1 mode, or it is asserted on the request of F-bit in T1/J1 mode. The RSCFS is sampled on the active edge of the RSCCK. MRSCFS: Multiplexed Receive Side System Common Frame Pulse When the multiplexed bus structure is configured, the signal on this pin aligns the multiplexed frame to the backplane timing. The MRSCFS is sampled on the active edge of the MRSCCK.
RSCCK/MRSCCK
Input
120
A5
RSCFS/MRSCFS
Input
119
B5
16
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name TSD[1]/MTSD[1] TSD[2]/MTSD[2] TSD[3] TSD[4] TSD[5] TSD[6] TSD[7] TSD[8] TSFS[1]/TSSIG[1]/ MTSSIG[1] TSFS[2]/TSSIG[2]/ MTSSIG[2] TSFS[3]/TSSIG[3] TSFS[4]/TSSIG[4] TSFS[5]/TSSIG[5] TSFS[6]/TSSIG[6] TSFS[7]/TSSIG[7] TSFS[8]/TSSIG[8] Type Input Pin No. PQFP PBGA B7 115 D6 113 A8 111 D7 109 B9 105 A11 103 A12 101 B11 99 114 112 110 106 104 102 100 98 A7 B8 C7 A10 D8 B10 C9 C10 Description TSD[1:8]: Transmit Side System Data for Framer 1 ~ 8 The data streams from the system backplane are input on these pins. In Transmit Clock Master mode, the TSDn is sampled on the active edge of the corresponding LTCKn. In Transmit Clock Slave mode, the TSDn is sampled on the active edge of the TSCCKB. MTSD[1:2]: Multiplexed Transmit Side System Data When the multiplexed bus structure is configured, the data stream from the backplane is carried on the multiplexed bus for the selected framers. The MTSD[1:2] are sampled on the active edge of the MTSCCKB. TSFS[1:8]: Transmit Side System Frame Pulse for Framer 1 ~ 8 In Transmit Clock Master mode, the TSFSn indicates the beginning of each Basic Frame in E1 mode, or indicates the F-bit of SF/ESF in T1/J1 mode. The TSFSn is updated on the active edge of the corresponding LTCKn. In Transmit Clock Slave TSFS Enabled mode, the TSFSn indicates the beginning of each Basic Frame in E1 mode, or indicates the F-bit of SF/ESF in T1/J1 mode. The TSFSn is updated on the active edge of the TSCCKB. TSSIG[1:8]: Transmit Side System Signaling for Framer 1 ~ 8 In Transmit Clock Slave External Signaling mode, these are the TSSIG inputs. The signaling is located in the lower nibble (b5 ~ b8) and sampled on the active edge of the TSCCKB. In E1 mode, the signaling repeats during the entire Signaling Multi-Frame for the same timeslot. In T1/J1 mode, the signaling repeats during the entire SF/ESF for the same channel. MTSSIG[1:2]: Multiplexed Transmit Side System Signaling When the multiplexed bus structure is configured, the signaling on the bus is organized in a byte-interleaved scheme for the selected framers. The MTSSIG[1:2] are sampled on the active edge of the MTSCCKB. TSCCKA: Transmit Side System Common Clock A TSCCKA is one of the reference clocks for the transmit jitter attenuator DPLL. TSCCKA can be configured to input the clock as: 1. 16.384MHz clock; 2. Line rate: 2.048MHz (for E1) or 1.544MHz (for T1); 3. Nx8KHz (N is from 1 to 256) so long as TSCCKA is a jitter-free clock. The IDT82V2108 can be configured to ignore the TSCCKA and utilize LRCK and TSCCKB instead. The TSCCKA is replaced by LRCK if line loopback is enabled. TSCCKB: Transmit Side System Common Clock B In E1 mode, the TSCCKB is a 2.048 or 4.096 MHz clock. In T1/J1 mode, the TSCCKB is a 1.544 or 2.048 or 4.096 MHz clock. In Transmit Clock Slave TSFS mode, the TSDn and TSCFS are sampled and the TSFSn is updated on the active edge of the TSCCKB. In Transmit Clock Slave External Signaling mode, the TSDn, TSSIGn and TSCFS are sampled on the active edge of the TSCCKB. MTSCCKB: Multiplexed Transmit Side System Common Clock B When the multiplexed bus structure is configured, MTSCCKB is an 8.192 or 16.384 MHz reference clock for the transmit system multiplexed bus. The MTSCFS, the MTSD[1:2] and the MTSSIG[1:2] are sampled on the active edge of the MTSCCKB.
Output /Input
TSCCKA
Input
123
A4
TSCCKB/ MTSCCKB
Input
122
B4
17
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name TSCFS/ MTSCFS Type Input Pin No. PQFP PBGA 121 C5 Description TSCFS: Transmit Side System Common Frame Pulse In Transmit Clock Slave mode, TSCFS is used to frame align all the framers to the system backplane. In E1 mode, the pulse can be configured to indicate the first bit of a Basic Frame, CRC Multi -Frame / Signaling Multi-Frame. In T1/J1 mode, the pulse can be configured to indicate the first bit of SF/ESF. The width of the pulse must be at least 1 TSCCKB cycle wide. The TSCFS is sampled on the active edge of the TSCCKB. MTSCFS: Multiplexed Transmit Side System Common Frame Pulse When the multiplexed bus structure is configured, MTSCFS is used to frame align the multiplexed frames to the system backplane. The MTSCFS is sampled on the active edge of the MTSCCKB. LTD[1:8]: Line Transmit Data for Framer 1 ~ 8 These pins output the data stream to line interface units or a higher multiplex interface. The data on the LTDn is updated on the active edge of the corresponding LTCKn.
LTD[1] LTD[2] LTD[3] LTD[4] LTD[5] LTD[6] LTD[7] LTD[8] LTCK[1] LTCK[2] LTCK[3] LTCK[4] LTCK[5] LTCK[6] LTCK[7] LTCK[8] XCK
Output
Output
Input
9 11 13 15 22 24 26 28 10 12 14 16 23 25 27 29 117
D2 E3 F4 E1 G3 H1 J2 J3 C1 D1 F3 E2 H2 H3 J1 H4 B6
LTCKn: Line Transmit Clock for Framer 1 ~ 8 It is a nominal E1 (2.048MHz) or T1/J1 (1.544MHz) clock. The LTCK can be derived from TSCCKA, TSCCKB, LRCK or XCK. On the active edge of the LTCKn, the corresponding LTDn is updated.
RST CS
Input
39
M2
Input
65
M11
INT A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]
Output Input
40 54 55 56 57 58 59 60 61 62 63 64
J5 K7 L8 M8 K8 L9 M9 K9 J8 M10 J9 L10
XCK: Crystal Clock The clock frequency equals 49.152MHz + 50 ppm 50% duty cycle for E1 and 37.056MHz + 32 ppm 50% duty cycle for T1/J1. Microprocessor Interface RST : Reset (Active Low) A low signal for at least 100ns on this pin can reset the device anytime. The RST is a Schmitttrigger input with weak pull-up. CS: Chip Select (Active Low) This pin must be asserted low to enable the microprocessor interface. The signal must be asserted high at least once after power up to clear the internal test modes. A transition from high to low must occur on this pin for each Read/Write operation and cannot return to high until the operation is over. INT: Open-Drain Interrupt Signal (Active Low) This pin will keep low until all the active unmasked interrupt are acknowledged at their sources. A[10:0]: Address Bus The signals on these pins select the register for the microprocessor to access.
18
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] RD WR ALE Type I/O Pin No. PQFP PBGA L4 41 M3 42 K5 43 M4 44 J6 45 K6 46 M5 47 L5 48 67 L11 66 53 K10 L7 Description D[7:0]: Bi-directional Data Bus Signals on these pins are the data for Read/Write operation.
Input Input Input
TRST
Input
125
D5
TMS TCK
Input Input
128 126
B3 A3
TDI TDO
Input Tri-State
127 124
D4 C4
BIAS
Power
17
G4
VDDIO[0] VDDIO[1] VDDIO[2] VDDIO[3]
Power
18 49 74 107
F1 J7 K12 D10
RD: Read Strobe (Active Low) A low signal on this pin enables a read operation on the selected register. WR: Write Strobe (Active Low) A low signal on this pin enables a write operation on the selected register. ALE: Address Latch Enable In non-multiplexed address/data bus, the ALE is connected to High. It is internally pulled-up. JTAG Signals (per IEEE 1149.1) TRST : Test Reset (Active Low) A low signal on this pin will reset the JTAG test port anytime. This pin is a Schmitt-triggered input with an internal pull-up resistor. It must be connected to the RST pin or ground when JTAG is not used. TMS: Test Mode Select The signal on this pin controls the JTAG test performance and is clocked into the device on the rising edge of the TCK. This pin has an internal pull-up resistor. TCK: Test Clock The clock for the JTAG test is input on this pin. The TDI and the TMS are clocked into the device on the rising edge of the TCK and the TDO is clocked out of the device on the falling edge of the TCK. TDI: Test Input The test data are input on this pin. It is sampled on the rising edge of the TCK. This pin has an internal pull-up resistor. TDO: Test Output The test data are output on this pin. It is sampled on the falling edge of the TCK. This pin is in tri-state mode, except during the process of scanning of the data. Supplies and Grounds BIAS: +5V Bias This pin enables +5V tolerance on the inputs. When +5V tolerance inputs are required, the BIAS must be connected to a well-decoupled +5V rail. When +3V input is required, the BIAS must be connected to a well-decoupled +3.3V DC supply. During power up, the power should be applied to the BIAS pin before any of VDDC/VDDIO pins is powered. VDDIO[3:0]: These pins must be connected to a common, well-decoupled +3.3V DC supply together with the core power pins VDDC[4:0] externally.
19
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name VDDC[0] VDDC[1] VDDC[2] VDDC[3] VDDC[4] VDDC[5:12] Type Power Pin No. PQFP PBGA G1 20 L6 51 F11 85 A6 92 C8 116 E8, E7, E6, E5, F8, F7, F6, F5 F2 19 K1 50 M6 75 E9 30 G2 21 M7 52 F10 86 C6 93 A9 118 G8, G7, G6, G5, H8, H7, H6, H5 108 H10 Description VDDC[4:0]: These pins must be connected to a common, well-decoupled +3.3V DC supply together with the pad ring power pins VDDIO[3:0] externally. The VDDC[5:12] are extra power pins for PBGA.
GNDIO[0] GNDIO[1] GNDIO[2] GNDIO[3] GNDC[0] GNDC[1] GNDC[2] GNDC[3] GNDC[4] GNDC[5:12]
Ground
GNDIO[3:0]: These pins must be connected to a common ground together with the core ground pins GNDC[4:0]. GNDC[4:0]: These pins must be connected to a common ground together with the pad ring ground pins GNDIO[3:0]. The GNDC[5:12] are extra ground pins for PBGA.
Ground
TESTSE
Input
This pin is connected to ground for normal operation and reserved for testing.
Notes: 1. All outputs have 4mA drive capability except for the D[7:0], the LTCK[1:8] and the RSCK[1:8] pins which have 6mA drive capability. 2. All input and bi-directional pins present minimum capacitive loading.
20
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3
3.1
FUNCTIONAL DESCRIPTION
T1 / E1 / J1 MODE SELECTION
The IDT82V2108 can be configured as a duplex eight ports E1 framer, or a duplex eight ports T1 framer, or a duplex eight ports J1 framer. When the TMODE (b0, 400H)* is set to 0, the device is in E1 mode. When the TMODE (b0, 400H) is set to 1, the device is in T1/J1 mode (default mode). In T1/J1 mode, when the JYEL (b3, T1/J1-020H) and the J1_YEL (b5, T1/J1-02CH) are both set to 0, the receive path of the corresponding framer is in T1 mode; when the JYEL (b3, T1/J1020H) and the J1_YEL (b5, T1/J1-02CH) are both set to 1, the receive path of the corresponding framer is in J1 mode; when the J1_CRC (b6, T1/J1-044H) and the J1_YEL (b5, T1/J1-044H) are both set to 0, the transmit path of the corresponding framer is in T1 mode; when the J1_CRC (b6, T1/J1-044H) and the J1_YEL (b5, T1/J1-044H) are both set to 1, the transmit path of the corresponding framer is in J1 mode.
condition has persisted for at least 100 ms, an AIS Alarm is declared. The Frame Processor can also declare a Red Alarm if the out-of-frame condition has persisted for at least 100 ms. An interrupt output is provided to indicate status changes and the occurrence of some events. The interrupts may be generated every Basic Frame, CRC Sub Multi-Frame, CRC Multi-Frame or Signaling Multi-Frame. The Frame Processor can also be bypassed to receive unframed data. Basic Frame The algorithm of searching for the E1 Basic Frame alignment pattern (as shown in Figure - 2) meets the ITU-T Recommendation G.706 4.1.2 and 4.2. Generally, it is performed by detecting a successive FAS/NFAS/FAS sequence. If STEP 2 is not met, a new search will start after the following frame is skipped. If STEP 3 is not met, a new search will start immediately in the next frame. Once the Basic Frame alignment pattern is detected in the received PCM data stream, the Basic Frame synchronization is found and the OOFV (b6, E1-036H) will be set to logic 0 for indication. Then, this block goes on monitoring the received data stream. If the received Basic Frame alignment signal does not meet its pattern, it will be indicated by setting the FERI (b2, E1-034H). The criteria of out of Basic Frame synchronization are selected by the BIT2C (b6, E1-031H). If one of the conditions that set in the BIT2C (b6, E1-031H) is met, the search process will restart when the REFRDIS (b0, E1-030H) is 0. Excessive CRC errors will also lead to re-searching for the Basic Frame (refer to "CRC Multi-Frame" for details). However, the Basic Frame synchronization can also be forced to research for a new Basic Frame any time when there is a transition from 0 to 1 on the REFR (b2, E1-030H). CRC Multi-Frame The CRC Multi-Frame is provided to enhance the ability of verifying the data stream. The structure of TS0 of CRC Multi-Frame is illustrated in Table - 1: A CRC Multi-Frame consists of 16 continuous Basic Frames (No. 0 - 15) which are numbered from a Basic Frame with FAS. Each CRC MultiFrame can be divided into two Sub Multi-Frames (SMF I & SMF II). The first bit of TS0 of each frame is called International (Si) bit. The Si bit in each even frame is the CRC bit. Thus, there are C1, C2, C3, C4 in each SMF. The C1 is the most significant bit, while the C4 is the least significant bit. The Si bit in the first six odd frames is the CRC MultiFrame alignment pattern. Its pattern is `001011'. The Si bit in the Frame 13 and the Frame 15 are E1 and E2 bits. The E bits' value can indicate the Far End Block Errors (FEBE). After the Basic Frame has been synchronized, the Frame Processor initiates an 8 and 400ms timer to check the CRC Multi-Frame alignment signal if the CRCEN (b7, E1-030H) is 1. The CRC Multi-Frame synchronization is declared with a logic 0 in the OOCMFV (b4, E1-036H) only if at least two CRC Multi-Frame alignment patterns are found within 8ms, with the interval time of each pattern being a multiple of 2ms. Then if the received CRC Multi-Frame alignment signal does not meet its pattern, it will be indicated by the CMFERI (b0, E1-034H). The Frame Processor calculates the data in the SMF(N) per the algorithm in the G.704 and the G.706 to get a four-bit remainder, then compares the four-bit remainder with the C1, C2, C3, C4 in the next SMF. If there is a difference between
3.2
FRAME PROCESSOR (FRMP)
The Frame Processor of each framer operates independently. 3.2.1 E1 MODE In E1 mode, the Frame Processor searches for Basic Frame synchronization, CRC Multi-frame synchronization, and Channel Associated Signaling (CAS) Multi-frame synchronization in the received data stream. Figure - 1 shows the searching process. Once the frame is synchronized, the Frame Processor keeps on monitoring the received data stream. If there are any framing bit errors, CAS Multi-Frame alignment pattern errors, CRC Multi-Frame alignment pattern errors or CRC errors, the Frame Processor will indicate these errors. The status of loss of frame, loss of Signaling Multi-Frame and loss of CRC Multi-Frame can also be detected and declared based on user-selectable criteria. The reframe operation can be initiated by excessive CRC errors, or the CRC Multi-Frame alignment is not found within 400ms. A software reset can also make the Frame Processor reframe. The Frame Processor can extract the data stream in TS16, and output the extracted data on a separate pin. The Frame Processor also extracts the contents of the International bits (from both the FAS and the NFAS frames), the National bits and the Extra bits (from TS16 in the frame 0 of the Signaling Multi-Frame), and stores these data in registers. The CRC Sub Multi-Frame alignment 4 bit codeword in the National bit positions Sa4 to Sa8 can also be extracted and stored in registers, and updated every CRC Sub Multi-Frame. The Framer Processor identifies the Remote Alarm bit (bit 3 of TS0 of NFAS frames) and Remote Signaling Multi-Frame Alarm (bit 6 of TS16 of the frame 0 of the Signaling Multi-Frame). The "de-bounced" Remote Alarm and Remote Signaling Multi-Frame Alarm can be indicated if the corresponding bit has been a certain logic for consecutive 2 or 3 times. The AIS (Alarm Indication Signal) can also be detected, and if the AIS
Note: * The contents in the brackets indicate the position of this bit and the address of the register. If more than one register contains the same bit, the address is only for the first register, the addresses of the remaining registers are listed together with the first register in the Register Description paragraph.
21
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Out of sync. OOFV=1,OOCMFV=1, OOSMFV=1, OOOFV=0,RAI=1,Ei=0 search for Basic Fframe alignment patten (refer to Basic Frame) find FAS in Nth frame Yes No (N=N+1) 3 consecutive FAS or NFAS errors (criteria selected by the BIT2C) or manually re-frame
find NFAS in (N+1)th frame Yes
No (skip one frame, N=N+3)
find FAS in (N+2)th frame Yes > 914 CRC search for CRC Multi-Frame errors in alignment pattern if CRCEN = one 1 (refer to CRC Multi-Frame) second Start 8ms and 400ms timer No (N=N+3)
Basic Frame sync. acquired OOFV=0, RAI=0, Ei=0 Start to check FAS errors
search for Signaling Multi-Frame alignment if CASDIS = 1 (refer to Signaling Multi-Frame) find Signaling Multi-Frame alignment pattern No Yes
find 2 CRC Multi-Frame alignment patterns within 8ms, with the interval time of each pattern being a multiple of 2ms Yes CRC Multi-Frame sync. acquired; Start CRC and E-bits processing; OOCMFV=0, OOFV=0 CRC to CRC interworking
No, and 8ms expired
Lock the Sync. Position Start Offline Frame search OOOFV=1
Signaling Multi-Frame sync. acquired
find FAS in nth frame No (n = n+1) Yes find NFAS in (n+1)th frame No (skip one frame, n=n+3) Yes find FAS in th (n+2) frame Yes No (n=n+3)
check for out of Signaling Multi-Frame Sync conditions which criteria are set in the SMFASC & TS16C No Yes
Basic Frame sync. acquired OOOFV=0 Start 8ms timer No, and 8ms expired find 2 CRC Multi-Frame alignment patterns within 8ms, with the interval time of each pattern being a multiple of 2ms Yes No, and 400ms expired with basic frame sync.
C2NCIWV=1 CRC to non-CRC interworking Stop CRC processing E-bits set to logic 0
Figure - 1. E1 Frame Searching Process
22
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
STEP1: Search for 7-bit Frame Alignment Sequence (FAS) (X0011011) th in the N frame No (skip one frame, N=N+3) Yes No (N=N+1)
STEP 2: Find logic 1 in the 2nd bit of TS0 of the (N+1)th frame to ensure that this is a non-frame alignment sequence (NFAS) Yes STEP 3: Search for the correct 7-bit FAS (X0011011) th in the TS0 in the (N+2) frame Yes Basic Frame Synchronization Found No (N=N+3)
them, bit errors exist in SMF(N) and a CRC error is counted. The CRCERR[9:0] (b7~0, E1-039H & b1~0, E1-03AH) are used to indicate the CRC error numbers and are updated every second. Once the CRCERR[9:0] (b7~0, E1-039H & b1~0, E1-03AH) are updated, a logic 1 will be set in the NEWDATA (b6, E1-03AH) for indication. If the CRCERR[9:0] are over-written, the OVR (b7, E1-03AH) will be asserted. When more than 914 CRC errors occur in one second which is indicated in the EXCRCERR (b0, E1-031H, a new search for the Basic Frame alignment pattern will start if the REFCRCE (b1, E1-030H) is set to 1 and the REFRDIS (b0, E1-030H) is set to 0. If the 2 CRC Multi-Frame alignment patterns can not be found within 8ms with the interval time being a multiple of 2ms, an offline search for the Basic Frame alignment pattern will start which is indicated in the OOOFV (b3, E1-036H). The process is the same as shown in Figure - 2. This offline operation searches in parallel with the pre-found Basic Frame synchronization searching process. After the new Basic Frame synchronization is found by this offline search, the 8ms timer is restarted to check whether the two CRC Multi-Frame alignment patterns are found within 8ms, with the interval time of each pattern being a multiple of 2ms again. If the condition can not be met, the procedure will go on until the 400ms timer ends. If the condition still can not be met at that time and the Basic Frame is still synchronized, the device declares by the C2NCIWV (b7, E1-036) to run under the CRC to non-CRC interworking process. In this process, the CRC Multi-Frame alignment pattern can still be searched if the C2NCIWCK (b5, E1-030H) is logic 1. CAS Signaling Multi-Frame If the CRCEN (E1-030H) is logic 1, after the CRC Multi-Frame has been found, the Frame Processor starts to search for Signaling MultiFrame alignment pattern when the CASDIS (E1-030H) is logic 0. If the CRCEN is logic 0, after the Basic Frame has been found, the Frame Processor starts to search for Signaling Multi-Frame alignment signal when the CASDIS (E1-030H) is logic 0. Refer to Figure - 1. The Signaling Multi-Frame alignment pattern is located in the 1 - 4 bits of TS16 of Frame 0 of Signaling Multi-Frame. The pattern is `0000'. Once the pattern is detected, the Signaling Multi-Frame synchronization is acquired which is indicated with a logic 0 in the OOSMFV (b5, E1-
Figure - 2. Basic Frame Searching Process
Table - 1. The Structure Of TS0
SMF Basic Frame No. / Type 0 /FAS 1 / NFAS 2 / FAS 3 / NFAS 4 / FAS 5 / NFAS 6 / FAS 7 / NFAS 8 / FAS 9 / NFAS 10 / FAS 11 / NFAS 12 / FAS 13 / NFAS 14 / FAS 15 / NFAS the Eight Bits in Timeslot 0 4 5 1 1 Sa4 Sa5 1 1 Sa4 Sa5 1 1 Sa4 Sa5 1 1 Sa4 Sa5 1 1 Sa4 Sa5 1 1 Sa4 Sa5 1 1 Sa4 Sa5 1 1 Sa4 Sa5
SMF I
CRC-4 Multi-Frame
SMF II
1 (Si bit) C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 E1 C4 E2
2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
23
3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A
6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6
7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7
8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
036H). If the received Signaling Multi-Frame alignment signal does not meet its pattern, the SMFERI (b1, E1-034H) is set to logic 1. The entire content in TS16 of Frame 0 of Signaling Multi-Frame is `0000XYXX'. Y is for remote Signaling Multi-Frame alarm indication and X are extra bits. A new search of Signaling Multi-Frame alignment pattern is initiated when the out of the Signaling Multi-Frame criteria set in the SMFASC (b5, E1-031H) and the TS16C (b4, E1-031H) is met or when it is out of Basic Frame synchronization. All the above frame synchronization functions can only be executed when the UNF (b6, E1-000H) is logic 0. RED Alarm RED alarm is declared when the out of Basic Frame sync condition has persisted for 100ms. RED alarm is removed when the out of Basic Frame sync condition has been absent for 100ms. The RED alarm status is reflected in the RED (b3, E1-037H). The received data stream is out of Basic Frame sync when: 1) The Basic Frame has not been synchronized; 2) The received data stream meets the out of Basic Frame sync criteria set in the BIT2C (b6, E1031H); 3) There are excessive CRC errors in the received data stream. Any one of the three conditions will be indicated by the OOFV (b6, E1036H). The integration of RED alarm uses the following algorithm: The algorithm monitors the occurrence of out of Basic Frame over a 4ms interval. A valid out of Basic Frame presence is accumulated when one or more out of Basic Frame indications occurred during the 4ms interval. Each valid out of Basic Frame presence increases one accumulation. An invalid out of Basic Frame presence is also accumulated when there is no out of Basic Frame indication occurring during the 4ms inverval. Each invalid out of Basic Frame indication decreases one accumulation (until the accumulation is zero). The RED alarm is declared when 25 valid out of Basic Frame presences have been accumulated. The RED alarm is removed when the out of Basic Frame presences reaches 0. AIS Alarm The AIS density criteria are selected in the AISC (b1, E1-031H). That is, if it is out of Basic Frame synchronization and less than 3 zeros are detected in a 512-bit stream, or if it is out of Basic Frame synchronization and less than 3 zeros are detected in each of 2 consecutive 512-bit streams, the status will be reported by the AISD (b5, E1-037H). When the above status has lasted for 100ms, AIS alarm is declared with a logic 1 in the AIS (b2, E1-037H). However, in unframed mode, the detection of AIS alarm is disabled.
Bits Extraction The Frame Processor extracts the National Bit codeword (Sa4[1:4] to Sa8[1:4] in the CRC Sub Multi-frame), the International bit (Si), the National bit (Sa), the Remote Alarm Indication bit (A), the Extra bits (X) and the Remote Signaling Multi-Frame Alarm Indication bit (Y). - National Bit Codeword The Frame Processor extracts one of the National Bit codeword (Sa4[1:4] to Sa8[1:4] in the CRC Sub Multi-frame) to the SaX[1:4] (b3~0, E1-03DH). Here the `X' is selected from 4 to 8 by the SaSEL[2:0] (b7~5, E1-03BH). The SaX[1:4] (b3~0, E1-03DH) are debounced. They are updated only when two consecutive codewords are the same. - International Bit The International bits (Si) are extracted to the Si[1:0] (b7~6, E1038H). The Si[1:0] (b7~6, E1-038H) are updated on the boundary of the associated FAS/NFAS frame and are not updated when out of frame is reported. - National Bit The National bits (Sa) are extracted to the Sa[4:8] (b4~0, E1-038H). The Sa[4:8] (b4~0, E1-038H) are updated on the boundary of the associated NFAS frame and are not updated when out of frame is reported. - Remote Alarm Indication Bit The Remote Alarm Indication bit (A) is extracted to the A (b5, E1038H). The A (b5, E1-038H) is updated on the boundary of the associated NFAS frame. - Extra Bit The Extra bits (X) are extracted to the X[0:2] (b5 & b3~2, E1-03AH). The X[0:2] (b5 & b3~2, E1-03AH) are updated on the beginning of the Frame1 (next NFAS frame). - Remote Signaling Multi-Frame Alarm Indication Bit The Remote Signaling Multi-Frame Alarm Indication bit (Y) is extracted to the Y (b4, E1-03AH). The Y (b4, E1-03AH) is updated on the beginning of the Frame1 (next NFAS frame). V5.2 Link The V5.2 link ID signal, i.e. 2 out of 3 Sa7 bits being logic 0, is detected with the indication in the V52LINKV (b0, E1-036H). Interrupt Sources 24 kinds of interrupts are derived from this block as shown in Table 2. When there are conditions meeting the interrupt sources, the corresponding Status bit will be asserted high. When there is a transition (logic 1 to 0 or logic 0 to 1) on the Status bit, the corresponding Status Interrupt Indication bit will be set to logic 1 (If the Status bit does not exist, the source will cause its Status Interrupt Indication bit to logic 1 directly) and the Status Interrupt Indication bit will be cleared when it is read. A logic 1 in the Status Interrupt Indication bit means an interrupt occurred. The interrupt will be reported by the INT pin if its Status Interrupt Enable bit is logic 1.
24
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 2. Interrupt Sources In The E1 Frame Processor
No. 1 2 3 4 Sources The received Basic Frame alignment signal does not meet its pattern once Basic Frame sync is achieved. The received CRC Multi-Frame alignment signal does not meet its pattern once CRC Multi-Frame sync is achieved. The received Signaling Multi-Frame alignment signal does not meet its pattern once Signaling Multi-Frame sync is achieved. The received data stream is out of Basic Frame sync, that is, when: 1. The Basic Frame has not been synchronized; 2. The received data stream meets the out of Basic Frame sync criteria set in the BIT2C (b6, E1-031H); 3. There are excessive CRC errors in the received data stream. The received data stream is out of CRC Multi-Frame sync, that is, when: 1. The CRC Multi-Frame has not been synchronized; 2. There are excessive CRC errors in the received data stream. The received data stream is out of Signaling Multi-Frame sync, that is, when: 1. The received data stream is out of Basic Frame sync; 2. The received data stream meets the out of Signaling Multi-Frame sync criteria set in the SMFASC (b5, E1-031H) and the TS16C (b4, E1-031H). The out of Basic Frame sync condition has lasted for 100ms. (e.g. the condition in item No.4 has lasted for 100ms.) The calculated CRC remainder is not equal to the received C[1:4] bits. It is out of Basic Frame sync and less than 3 zeros are detected in a 512-bit stream, or it is out of Basic Frame sync and less than 3 zeros are detected in each of 2 consecutive 512-bit stream. These two criteria are selected in the AISC (b1, E1-031H). The condition in item No.9 has lasted for 100ms. Logic 1 is received in the A bit for a certain period. The criteria are defined in the RAIC (b3, E1-031H). Logic 0 is received in any of the CRC error indication (E1 or E2) bit. A logic 1 is received in the A bit and a logic 0 is received in any of the E1 or E2 bits for 10ms. A logic 0 is received in any of the E1 or E2 bits on 990 occasions per second for the latest 5 consecutive seconds. Logic 1 is received in the Y bit for 3 consecutive Signaling MultiFrames. The device is operating in the CRC to non-CRC inter working mode. The position of the Basic Frame alignment pattern is changed. The device is in the procedure of the offline Basic Frame searching. The first bit of each Basic Frame is received. The first bit of each CRC Sub Multi-Frame is received. The first bit of each CRC Multi-Frame is received. The first bit of each Signaling Multi-Frame is received. 2 out of 3 Sa7 bits are received as logic 0. There is change in the corresponding SaX[1:4] (b3~0, E1-03DH). Status Bit OOFV (b6, E1-036H) OOCMFV (b4, E1-036H) OOSMFV (b5, E1-036H) RED (b3, E1-037H) AISD (b5, E1-037H) AIS (b2, E1-037H) RAIV (b7, E1-037H) RAICCRCV (b2, E1-036H) CFEBEV (b1, E1-036H) RMAIV (b6, E1-037H) C2NCIWV (b7, E1-036H) OOOFV (b3, E1-036H) V52LINKV (b0, E1-036H) Interrupt Indication Bit FERI (b2, E1-034H) CMFERI (b0, E1-034H) SMFERI (b1, E1-034H) Interrupt Enable Bit FERE (b2, E1-032H) CMFERE (b0, E1-032H) SMFERE (b1, E1-032H) OOFE (b6, E1-032H)
OOFI (b6, E1-034H)
5 6
OOCMFI (b4, E1-034H)
OOCMFE (b4, E1-032H) OOSMFE (b5, E1-032H) REDE (b3, E1-033H) CRCEE (b0, E1-033H) AISDE (b5, E1-033H) AISE (b2, E1-033H) RAIE (b7, E1-033H) FEBEE (b1, E1-033H) RAICCRCE (b6, E1-03EH) CFEBEE (b5, E1-03EH) RMAIE (b6, E1-033H) C2NCIWE (b7, E1-032H) COFAE (b3, E1-032H) OOOFE (b7, E1-03EH) IFPE (b3, E1-03EH) ICSMFPE (b2, E1-03EH) ICMFPE (b1, E1-03EH) ISMFPE (b0, E1-03EH) V52LINKE (b4, E1-03EH) Sa4E, Sa5E, Sa6E, Sa7E, Sa8E (b4~0, E1-03BH)
OOSMFI (b5, E1-034H)
7 8 9
REDI (b3, E1-035H) CRCEI (b0, E1-035H) AISDI (b5, E1-035H) AISI (b2, E1-035H) RAII (b7, E1-035H) FEBEI (b1, E1-035H) RAICCRCI (b6, E1-03FH) CFEBEI (b5, E1-03FH) RMAII (b6, E1-035H) C2NCIWI (b7, E1-034H) COFAI (b3, E1-034H) OOOFI (b7, E1-03FH) IFPI (b3, E1-03FH) ICSMFPI (b2, E1-03FH) ICMFPI (b1, E1-03FH) ISMFPI (b0, E1-03FH) V52LINKI (b4, E1-03FH) Sa4I, Sa5I, Sa6I, Sa7I, Sa8I (b4~0, E1-03CH)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
25
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.2.2 T1/J1 MODE In T1/J1 Mode, the Frame Processor searches for the frame alignment patterns in the standard Super-Frame (SF) or in the Extended Super-Frame (ESF) framing formats. The format is selected by the ESF (b4, T1/J1-020H). The searching algorithm of T1 or J1 is selected by the JYEL (b3, T1/J1-020H). The Frame Processor acquires frame alignment per ITU-T requirement. When frame alignment is achieved, the Framer Processor continues to monitor the received data stream. If there are any of framing bit errors or bit error events, the Frame Processor declares these events. The Frame Processor can also detect out-of-frame events based on selectable criteria. The Frame Processor can also be disabled to receive unframed data. Super Frame (SF) Format The structure of T1/J1 SF format is illustrated in the Table - 3. The SF is made up of 12 frames. Each frame consists of a one bit overhead - F Bit and 24 8-bit channels. If two consecutive valid Frame Alignment Patterns - `100011011100' for T1 / `10001101110X' for J1 - are received in the F-Bit in the received data stream, the SF synchronization is acquired. If the same pattern is received in the data stream other than in the F-bit, it is a mimic pattern. If a mimic pattern exists during the frame searching procedure, the synchronization will not be declared and the MFP (b1, T1/J1-022H) will be set to indicate the presence of a mimic pattern. Extended Super Frame (ESF) Format The structure of T1/J1 ESF format is illustrated in the Table-4. The ESF is made up of 24 frames. Each frame consists of a one bit overhead - F Bit and 24 8-bit channels.
The pattern of the Frame Alignment Pattern is `001011', which is located from Frame 4 in every 4th F-bit position. When the ESFFA (b5, T1/ J1-020H) is set to 0, if four consecutive Frame Alignment Patterns are detected in the F-Bit in the received data stream, the ESF synchronization is acquired. If the same pattern is received in the data stream other than in the F-bit, it is a mimic pattern. If a mimic pattern exists during the frame searching procedure, the synchronization will not be declared and the MFP (b1, T1/J1-022H) will be set to indicate the presence of a mimic pattern. When the ESFFA (b5, T1/J1-020H) is set to 1, the synchronization will be declared when 6 consecutive Frame Alignment Patterns are received error free and the CRC-6 checksum is also error free. In this condition, the existance of mimic patterns will not be considered. A 4-frame capacity buffer is used to store the data when the Frame Processor is searching for SF/ESF synchronization. Once the SF/ESF is synchronized, the buffer is relinquished by the Frame Processor and the Frame Processor continues to monitor the errors. When the FAS error ratio exceeds the criteria configured in the M2O[1:0] (b7~6, T1/J1020H), it is out of frame. All the frame sync function can only be executed when the UNF (b6, T1/J1-000H) is logic 0. The interrupt sources in this block are summarized in Table - 5. When there are conditions meeting the interrupt sources, the corresponding Status bit will be asserted high. When there is a transition (logic 1 to 0 or logic 0 to 1) on the Status bit, the corresponding Status Interrupt Indication bit will be set to logic 1 (If the Status bit does not exist, the source will cause its Status Interrupt Indication bit to be logic 1 directly) and the Status Interrupt Indication bit will be cleared when it is read. A logic 1 in the Status Interrupt Indication bit indicates an interrupt occurred. The interrupt is reported by the INT pin if its Status Interrupt Enable bit was set to logic 1.
Table - 3. The Structure Of SF Format
The Bit In Each Channel Signaling Bit A (bit 8) B (bit 8)
Frame No. In The SF 1 2 3 4 5 6 7 8 9 10 11 12
F-Bit (Frame Alignment) 1 0 0 0 1 1 0 1 1 1 0 X
Data Bit 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7
X should be logic 0 in T1 FAS. X can be logic 0 or 1 in J1 FAS because this position is used as Yellow Alarm Indication bit.
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Table - 4. The Structure Of ESF Format
Frame No. In The ESF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 F-Bit Assignment DL DL DL DL DL DL DL DL DL DL DL DL DL The Bit In Each Channel Data Bit Signaling Bit 1-8 1-8 1-8 1-8 1-8 1-7 A (bit 8) 1-8 1-8 1-8 1-8 1-8 1-7 B (bit 8) 1-8 1-8 1-8 1-8 1-8 1-7 C (bit 8) 1-8 1-8 1-8 1-8 1-8 1-7 D (bit 8)
FAS 0 0 1 0 1 1
CRC C1 C2 C3 C4 C5 C6 -
Table - 5. Interrupt Sources In The T1 / J1 Frame Processor
No. 1 2 3 4 5 6 Sources The frame alignment mimic pattern is detected in the received data stream. The SF / ESF synchronization is found. The position of the new frame alignment pattern differs from . the position of the previous one. One bit error is detected in frame alignment pattern. Two or more bit errors are detected in one frame alignment pattern. In the SF format, one bit error is detected in frame alignment pattern. In the ESF format, the received CRC-6 is not equal to the local calculated CRC-6. Status Bit MFP (b1, T1/J1-022H) INFR (b0, T1/J1-022H) Interrupt Indication Bit MFPI (b3, T1/J1-022H) INFRI (b2, T1/J1-022H) COFAI (b7, T1/J1-022H) FERI (b6, T1/J1-022H) SFEI (b4, T1/J1-022H) BEEI (b5, T1/J1-022H) Interrupt Enable Bit MFPE (b1, T1/J1-021H) INFRE (b0, T1/J1-021H) COFAE (b5, T1/J1-021H) FERE (b4, T1/J1-021H) SFEE (b2, T1/J1-021H) BEEE (b3, T1/J1-021H)
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3.3
PERFORMANCE MONITOR (PMON)
The Performance Monitor is used to count various performance events in the received data stream within defined intervals. The Performance Monitor of each framer operates independently. 3.3.1 E1 MODE The PMON block counts the Basic Frame alignment pattern errors. The method of counting the errors is defined by the WORDERR (b5, E1000H) and CNTNFAS (b4, E1-000H) as shown in Table - 6. The number of the Basic Frame alignment pattern errors counted during the interval is reflected in the FER[6:0] (b6~0, E1-069H). Table - 6. Basic Frame Alignment Pattern Error Counter
WORDERR (b5, E1-000H) 0 0 1 1 CNTNFAS (b4, E1-000H) 0 1 0 1 One Error is Counted One bit error in FAS One bit error in FAS or a logic 0 in bit 2 of TS0 of NFAS One or more than one bit error in a FAS Any bit error in a FAS and the 2nd bit of TS0 of the following NFAS
The PMON block counts the Far End Block Error (FEBE) which is detected in the E1 and E2 bits. The number of the FEBE counted during the interval is stored in the FEBE[9:0] (b1~0, E1-06BH & b7~0, E106AH). The block also counts the CRC errors which mean the local calculated CRC remainders are not equal to the received CRC. The number of the CRC errors counted during the interval is indicated in the CRCE[9:0] (b1~0, E1-06DH & b7~0, E1-06CH). The above three kinds of PMON Error Count registers are deactivated when the framer is out of Basic Framer synchronization. The latter two kinds of PMON Error Count registers are also deactivated when it is out of CRC Multi-Frame synchronization. These PMON Error Count registers in a framer can be updated as a group. The intervals are typically 1 second when the AUTOUPDATE (b0, E1-000H) of the current framer is set. They can also be updated by writing to any of these PMON Error Count registers. The PMON Error Count registers in eight framers can also be updated together by writing to the Revision / Chip ID / Global PMON Update register (E1-009H). Once the PMON Error Count registers are updated, the XFER (b1, E1-068H) will be set to logic 1 and an interrupt can be asserted on the INT pin if the INTE (b2, E1-068H) is logic 1. If the performance number counted in the next interval is latched in its PMON Error Count register without the previous one being read, the PMON Error Count register is over-written. Any over-writing of the three kinds of PMON Error Count registers will be indicated in the OVR (b0, E1-068H). 3.3.2 T1/J1 MODE In SF format, the Performance Monitor counts three kinds of events: 1. Every one-bit error in a frame alignment pattern is counted. The number of the errors counted during the interval is reflected in the
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FER[8:0] (b0, T1/J1-04DH & b7~0, T1/J1-04CH) (In SF format, the usage of the BEE[11:0] (b3~0, T1/J1-04BH & b7~0, T1/J1-04AH) is the same as that of the FER[8:0]); 2. The out of SF synchronization event is counted. The number counted during the interval is reflected in the OOF[4:0] (b4~0, T1/J104EH); 3. The number of changes of the frame alignment position during the interval is counted and is reflected in the COFA[2:0] (b2~0, T1/J1-04FH). In ESF format, the Performance Monitor counts four kinds of events: 1. The block counts the CRC-6 errors which mean the local calculated CRC-6 remainders are not equal to the received CRC-6. The number of the errors counted during the interval is indicated in the BEE[11:0] (b3~0, T1/J1-04BH & b7~0, T1/J1-04AH); 2 ~ 4. (The same events as 1 ~ 3 in the SF format, described above.) These PMON Error Count registers in a framer can be updated as a group. The intervals are typically 1 second when the AUTOUPDATE (b0, T1/J1-000H) of the framer is set. They can also be updated by writing to any of these PMON Error Count registers. The PMON Error Count registers of eight framers can also be updated together by writing to the Revision / Chip ID / Global PMON Update register (T1/J1-00CH). Once the PMON Error Count registers are updated, the XFER (b1, T1/J1-049H) will be logic 1 and an interrupt can be asserted on the INT pin if the INTE (b2, T1/J1-049H) is logic 1. If the performance number counted in the next interval is latched in its PMON register without the previous one being read, the PMON Error Count register is over-written. Any over-writing of the four kinds of PMON Error Count registers will be indicated in the OVR (b0, T1/J1049H).
3.4
ALARM DETECTOR (ALMD) - T1 / J1 ONLY
The Alarm Detector block exists in T1/J1 mode only. It detects the Yellow signal and the AIS (Blue Alarm) signal in SF/ESF in T1/J1 data stream and declares the Yellow alarm, the Red alarm and the AIS alarm. The T1 or J1 mode is selected by the J1_YEL (b5, T1/J1-02CH) while the SF or ESF format is selected by the ESF (b4, T1/J1-02CH). The Yellow signal is declared differently in each format: - In T1 SF format: The Yellow signal occupies the 2nd bit of each channel. When the occurence of logic 1 in this bit position is less than 16 times (including 16 times) during a 40ms period, the Yellow signal is declared. - In J1 SF format: The Yellow signal occupies the F-bit of the 12th frame. When the occurence of logic 0 on this bit position is less than 2 times (including 2 times) during a 40ms period, the Yellow signal is declared. - In T1/J1 ESF format: The Yellow signal occupies the DL of the F-bit (refer to Table-4). The pattern is `FF00' in T1 mode and `FFFF' in J1 mode. When the AVC (b1, T1/J1-02AH) is logic 0, the Yellow signal is declared if 8 out of 10 successive patterns match the `FF00' (in T1) or `FFFF' (in J1) on the DL bit position. When the AVC (b1, T1/J1-02AH) is logic 1, the Yellow signal is declared if 4 out of 5 successive patterns match the `FF00' (in T1) or `FFFF' (in J1) on the DL bit position Any of the above conditions will be indicated by the YELD (b1, T1/J102FH). The AIS signal is declared when the received data are out of SF/ESF synchronization for 60ms and the received logic 0 is less than 127 times in the same period. Then the AIS signal will be indicated by the AISD (b0, T1/J1-02FH).
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The Red signal is declared when one or more out of SF/ESF sync event occurs in 40ms. Then the Red signal will be indicated by the REDD (b2, T1/J1-02FH). The Yellow alarm, AIS alarm and Red alarm will be declared or cleared when the corresponding alarm signal is present or absent for a certain period as summarized in Table - 7. The Yellow alarm, AIS alarm and Red alarm are also the interrupt sources in the ALMD block. When the alarm occurs, the corresponding Interrupt Status Register (YEL, AIS or RED in b2, b0, b1 of T1/J1-02EH respectively) will indicate it. When there is any transition (from 0 to 1 or from 1 to 0) on the Interrupt Status Register, its corresponding Interrupt Indication Register (YELI, AISI or REDI in b5, b3, b4 of T1/J1-02EH respectively) will be logic 1. A transition on the Interrupt Indication Register can cause an interrupt on the INT pin if the corresponding Interrupt Enabled Register (YELE, AISE or REDE in b2, b0, b1 of T1/J1-02DH respectively) is logic 1.
timeslot except TS16); 3. Sa-bit data link. All the functions of the selected HDLC Receiver block can be enabled only if the EN (b0, E1-048H) is set to logic 1. A normal HDLC packet consists of the following parts as shown in Figure - 3:
Flag (7E) one byte 01111110 HDLC Data n bytes n2 FCS two bytes Flag (7E) one byte 01111110
(remove the stuffed zero) store in FIFO
3.5
HDLC RECEIVER (RHDLC)
Figure - 3. HDLC Packet Every HDLC packet starts with a 7E (Hex) opening flag sequence and ends with the same flag. Before the closing flag sequence, two bytes of CRC-CCITT frame check sequences (FCS) are provided to check all the HDLC data. The received FCS will be compared with the local calculated FCS. A FIFO buffer is used to store the HDLC packet, that is, to store the data whose stuffed zeros have been removed and the FCS. However, when the address matching is enabled, the first and/or second byte compares with the address setting in the PA[7:0] (b7~0, E1-04CH) and the SA[7:0] (b7~0, E1-04DH), and only the data matching the selection in the MEN (b3, E1-048H) and the MM (b2, E1-048H) are stored into the FIFO. When address matching is disabled, all the HDLC data are stored. The first 7E opening flag which activates the HDLC link and the 7F (Hex) abort sequence which deactivates the HDLC link will also be converted to dummy bytes and stored into the FIFO regardless if the address is matching or not. These two types of flags will also assert the COLS (b5, E1-04AH) to indicate the HDLC link status change. The content in the FIFO is read in the RD[7:0] (b7~0, E1-04BH), and the status of the bytes will be reflected in the PBS[2:0] (b3~1, E1-04AH). Both of these registers (RD[7:0] (b7~0, E1-04BH) and PBS[2:0] (b3~1, E1-04AH)) can not be accessed at a rate greater than 1/15 of the XCK rate. The depth of the FIFO is 128 bytes. When the FIFO is empty, the FE (b7, E1-04AH) will be set. If data are still written into the FIFO when the FIFO is already full, the FIFO will be over-written. The over-written condition will be indicated by the OVR (b6, E1-04AH) and forces the FIFO to be cleared. A logic 1 in the PKIN (b4, E1-04AH) indicates a non-abort HDLC
The HDLC extraction is performed in this block. The HDLC Receiver #1, #2 and #3 in E1 mode or the HDLC Receiver #1 and #2 in T1/J1 ESF mode of each framer operate independently. 3.5.1 E1 MODE Three HDLC Receiver blocks (#1, #2 and #3) are employed for each framer to extract the HDLC link from the received data stream. Before selecting the HDLC link, the TXCISEL (b3, E1-00AH) should be set to 0. Thus, the configuration of the Link Control and Bits Select registers (addressed from 028H to 02DH) is for RHDLC. Next, select one of the three HDLC Receiver blocks by selecting the appropriate bits in the RHDLCSEL[1:0] (b7~6, E1-00AH). The #2 and #3 blocks can also be disabled by setting the V52DIS (b3, E1-007H). Then the position of the HDLC link can be defined as follows: 1. Set the DL_EVEN (b7, E1-028H or b7, E1-02AH or b7, E1-02CH) and/or the DL_ODD (b6, E1-028H or b6, E1-02AH or b6, E1-02CH) to select the even and/or odd frames (the even frames are FAS frames while the odd frames are NFAS frames); 2. Set the DL_TS[4:0] (b4~0, E1-028H or b4~0, E1-02AH or b4~0, E1-02CH) to define the timeslot of the assigned frame (or to select the TS16_EN (b5, E1-028H) to select the TS16 of the assigned frame); 3. Set the DL_BIT[7:0] (b7~0, E1-029H or b7~0, E1-02BH or b7~0, E1-02DH) to select the bits of the assigned timeslot. Three HDLC standards for E1 are defined and one is selected as follows: 1. Common Channel Signaling (CCS) data link (extract the bits in the TS16); 2. V5.1 / V5.2 D-channel and C-channels (extract the bits in any
Table - 7. Alarm Summary in ALMD Declaring the Yellow signal is present for 425ms ( 50ms) the AIS signal is present for 1.5sec ( 100ms) the Red signal is present for 2.55sec ( 40ms)
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Yellow Alarm AIS Alarm Red Alarm
Clearing the Yellow signal is absent for 425ms ( 50ms) the AIS signal is absent for 16.8sec ( 500ms); or the AIS signal is absent for 180ms if the FASTD (b4, T1/J1-02DH) is set the Red signal is absent for 16.6sec ( 500ms); or the Red signal is absent for 120ms if the FASTD (b4, T1/J1-02DH) is set
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
packet was received. This bit (PKIN) is set regardless of the status of the FCS condition or if there are an integer or non-integer number of bytes stored in the FIFO. The HDLC packet can be forced to terminate for four reasons: 1. The 7F abort sequence is received; 2. More than 15 successive logic ones are received in the data stream; 3. Set the TR (b1, E1-048H) to logic 1; 4. Set the EN (b0, E1-048H) from logic 1 to logic 0 and back to logic 1. All the above methods can deactivate the HDLC link immediately and the latter two means can also clean the FIFO and interrupts. A new search for the 7E opening flag is also initiated. The interrupt sources in this block are: 1. Receiving the first 7E opening flag sequence which terminates all ones data and activates the HDLC link; 2. Receiving the 7E closing flag sequence; 3. Receiving the abort sequence; 4. Exceeding the set point of the FIFO which is defined in the INTC[6:0] (b6~0, E1-049); 5. Over-writting the FIFO. Any one of the interrupt sources will assert the INTR (b0, E1-04AH) high. Then the INT pin will be low to report the interrupt if the INTE (b7, E1-049H) is logic 1. 3.5.2 T1 / J1 MODE In the SF format, there is no HDLC link. In the ESF format, two HDLC Receiver blocks (#1 and #2) are employed for each framer to extract the HDLC link. Before selecting the HDLC link, the TXCISEL (b3, T1/J1-00DH) should be set to 0. Thus, the configuration of the Link Control and Bits Select registers (addressed from 070H to 071H) is for the RHDLC. Then, selected by the RHDLCSEL[1:0] (b7~6, T1/J1-00DH), one of the two HDLC Receiver blocks are accessable to the microprocessor. The HDLC#1 extracts the HDLC link in the DL of the F-bit (its position is shown in Table - 4). The HDLC#2 extracts the HDLC link from one of the channels which position is selected as follows: 1. Set the DL2_EVEN (b7, T1/J1-070H) and/or the DL2_ODD (b6, T1/J1-070H) to select the even and/or odd frames; 2. Set the DL2_TS[4:0] (b4~0, T1/J1-070H) to select the channel of the assigned frame; 3. Set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to select the bits of the assigned channel. All the functions of the selected HDLC Receiver block can be enabled only if the EN (b0, T1/J1-054H) is set to logic 1. The structure of the HDLC packet is the same as it is described in the E1 mode (refer to Figure - 3). A FIFO buffer is used to store the HDLC packet, that is, to store the data whose stuffed zeros have been removed and the FCS. However, when the address matching is enabled, the first and/or second byte compares with the address setting in the PA[7:0] (b7~0, T1/J1-058H) and the SA[7:0] (b7~0, T1/J1-059H) and only the data matching the selection in the MEN (b3, T1/J1-054H) and the MM (b2, T1/J1-054H) are stored into the FIFO. When the address matching is disabled, the entire HDLC packet is stored. The first 7E opening flag which activates the HDLC link and the 7F abort sequence which deactivates the HDLC link will also be converted into dummy bytes and stored in the FIFO. These
two types of flags will also assert the COLS (b5, T1/J1-056H) to indicate the HDLC link status change. The content in the FIFO is read in the RD[7:0] (b7~0, T1/J1-057H), and the status of the bytes will be reflected in the PBS[2:0] (b3~1, T1/J1-056H). Both of the two registers can't be accessed at a rate greater than 1/15 of the XCK rate. The depth of the FIFO is 128 bytes. When the FIFO is empty, the FE (b7, T1/J1-056H) will be set. If data are still written into the FIFO when the FIFO is already full, the FIFO will be over-written. The over-written condition will be indicated by the OVR (b6, T1/J1-056H) and force the FIFO to be cleared. A logic 1 in the PKIN (b4, T1/J1-056H) indicates a non-abort HDLC packet was received whether there were FCS errors or non-integer number if bytes errors in it or not. The HDLC packet can be forced to terminate by four means: 1. The 7F abort sequence is received; 2. More than 15 successive logic ones are received in the data stream; 3. Set the TR (b2, T1/J1-054H) to logic 1; 4. Set the EN (b1, T1/J1-054H) from logic 1 to logic 0 and back to logic 1. All the above methods can deactivate the HDLC link immediately and the latter two methods can also clear the FIFO and interrupts. A new search for the 7E opening flag is also initiated. The interrupt sources in this block are: 1. Receiving the first 7E opening flag sequence which terminates the all ones data and activates the HDLC link; 2. Receiving the 7E closing flag sequence; 3. Receiving the abort sequence; 4. Exceeding the set point of the FIFO which is defined in the INTC[6:0] (b6~0, T1/J1-055H); 5. Over-writting the FIFO. Any one of the interrupt sources will assert the INTR (b0, T1/J1056H) high. Then the INT pin will be driven low to report the interrupt if the INTE (b7, T1/J1-055H) is logic 1.
3.6 BIT-ORIENTED MESSAGE RECEIVER (RBOM) - T1 / J1 ONLY
The Bit Oriented Message (BOM) can only be received in the ESF format in T1/J1 mode. The standard of the BOM is defined in ANSI T1.403 and in TR-TSY-000194. This block of each framer operates independently. The BOM pattern is `111111110XXXXXX0' which occupies the DL of the F-bit in the ESF format (refer to Table-4). The six `X's represent the message. The BOM is declared only when the pattern is matched and the received message is identical 4 out of 5 times or 8 out of 10 times. The identification time is selected by the AVC (b1, T1/J1-02AH). After the BOM is declared, the BOM is loaded into the BOC[5:0] (b5~0, T1/J102BH). However, the BOM does not include all ones code in both T1 and J1 mode. When the BOM is converted into non-BOM, the received data will be idle code. The pattern of the idle code is `FFFF' in T1 mode and `FF7E' in J1 mode. When the received data is 4 out of 5 times or 8 out of 10 times identical with the pattern, the idle code is declared. The identification time is selected by the AVC (b1, T1/J1-02AH). There are two interrupt sources in this block. When the BOM is declared, the BOCI (b6, T1/J1-02BH) will indicate it. When the idle code is declared, the IDLEI (b7, T1/J1-02BH) will indicate it. If the BOCE (b0,
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
will be repeated after it is read. When the read pointer crosses the next frame boundary, a controlled slip will occur with a logic 0 indicated in the SLIPD (b1, E1-059H). When the slip occurs, the SLIPI (b0, E1-059H) will indicate. An inter3.7 INBAND LOOPBACK CODE DETECTOR (IBCD) rupt on the INT pin will also occur if the SLIPE (b2, E1-059H) is set to T1 / J1 ONLY The Inband Loopback Code Detector can track loopback activate/de- logic 1. In Receive Clock Slave mode, if it is out of Basic Frame synchronizaactivate codes only in framed or unframed T1/J1 data stream. The tion, the idle code programmed in the D[7:0] (b7~0, E1-05AH) in the Inband Loopback Code Detector of each framer operates independently. The received data stream is compared with the target activate/deacti- Elastic Store Buffer can be set to replace the data if the TRKEN (b1, E1vate code whose length and the content are programmed in the 001H) is set to logic 1. In Receive Clock Master mode, the Elastic Store Buffer is bypassed ASEL[1:0] (b1~0, T1/J1-03CH) / DSEL[1:0] (b3~2, T1/J1-03CH) and the unless the device is in the Payload Loopback diagnosis mode. (Refer to ACT[7:0] (b7~0, T1/J1-03EH) / DACT[7:0] (b7~0, T1/J1-03FH) respectively. In framed mode, the F-bit can be selected by the IBCD_IDLE (b5, Payload Loopback Mode for details). T1/J1-000H) to compare with the target activate/deactivate code or not. T1 / J1 MODE In unframed mode, all 193 bits are compared with the target activate/de- 3.8.2 In Receive Clock Slave mode, a 2-basic-frame depth Elastic Store activate code. Whether the received data stream matches the target activate or deactivate code and repeats for a 39.8ms period, the LBACP Buffer is used to synchronize the incoming frames to the Receive Side (b7, T1/J1-03DH) or LBDCP (b6, T1/J1-03DH) will indicate the appear- System Common Clock derived from the RSCCK pin, and to the Reance of the corresponding code. 2, 20 or 200 bit-error tolerance within ceive Side System Common Frame Pulse derived from the RSCFS pin. each 39.8ms period is permitted by setting the IBCD_ERR[1:0] (b5~4, A write pointer is used to write the data to the Elastic Store Buffer, while T1/J1-03CH). However, even if the F-bit is compared, whether it is a read pointer is used to read the data from the Elastic Store Buffer. When the average frequency of the incoming data is greater than the matched or not, the result will not cause bit errors, that is, the compariaverage frequency of the Receive Side System Common Clock son result of the F-bit is passed over. When the received data stream matches the target activate/deacti- (RSCCK), the write pointer will be faster than the read pointer and the vate code and repeats for 5.1 sec, the LBA (b1, T1/J1-03DH) / LBD (b0, Elastic Store Buffer will be filled. So a frame will be deleted after its prior T1/J1-03DH) will indicate the detection of the inband loopback code. The frame is read. When the read pointer crosses the frame boundary, a code sequences detection and timing is compatible with the specifica- controlled slip will occur with a logic 1 indicated in the SLIPD (b1, T1/J101DH). tions in T1.403, TA-TSY-000312 and TR-TSY-000303. When the average frequency of the incoming data is less than the The status changes of the activate or deactivate code are the interaverage frequency of the RSCCK, the write pointer will be slower than rupt sources in the IBCD block. That is, when the value in the Status Register (LBA [b1, T1/J1-03DH] or LBD [b0, T1/J1-03DH]) changes, its the read pointer and the Elastic Store Buffer will be empty. The frame corresponding Interrupt Indication Register (LBAI [b3, T1/J1-03DH] or will be repeated after it is read. When the read pointer crosses the next LBDI [b2, T1/J1-03DH]) will be logic 1. A logic 1 on the Interrupt Indica- frame boundary, a controlled slip will occur with a logic 0 indicated in the tion Register will cause an interrupt on the INT pin if the corresponding SLIPD (b1, T1/J1-01DH). When the slip occurs, the SLIPI (b0, T1/J1-01DH) will indicate. An inInterrupt Enable Register (LBAE [b5, T1/J1-03DH] or LBDE [b4, T1/J1terrupt on the INT pin will also occur if the SLIPE (b2, T1/J1-01DH) is 03DH]) is logic 1. logic 1. In Receive Clock Slave mode, if it is out of SF/ESF sync, the idle 3.8 ELASTIC STORE BUFFER (ELSB) code programmed in the D[7:0] (b7~0, T1/J1-01EH) in the Elastic Store The Elastic Store Buffer of each framer operates independently. Buffer will replace the data of all channels automatically. In Receive Clock Master mode, the Elastic Store Buffer is bypassed 3.8.1 E1 MODE unless the device is in the payload loopback diagnosis mode. (Refer to In Receive Clock Slave mode, a 2-basic-frame depth Elastic Store Payload Loopback Mode for details). Buffer is used to synchronize the incoming frames to the Receive Side System Common Clock derived from the RSCCK pin, and to the Re3.9 RECEIVE CAS/RBS BUFFER (RCRB) ceive Side System Common Frame Pulse derived from the RSCFS pin. The Receive CAS/RBS Buffer of each framer operates independA write pointer is used to write the data to the Elastic Store Buffer, while ently. a read pointer is used to read the data from the Elastic Store Buffer. When the average frequency of the incoming data is greater than the E1 MODE average frequency of the Receive Side System Common Clock 3.9.1 In the Signaling Multi-Frame synchronization condition, the signaling (RSCCK), the write pointer will be faster than the read pointer and the Elastic Store Buffer will be filled. So a frame will be deleted after its prior bits are located in TS16, which is Channel Associated Signaling (CAS). frame is read. When the read pointer crosses the frame boundary, a Their arrangement in TS16 is shown in Figure - 4. When the RSCKn/RSSIGn/MRSSIG[1:2] pins are used as the controlled slip will occur with a logic 1 indicated in the SLIPD (b1, E1signaling output, i.e. in Receive Clock Slave External Signaling mode or 059H). When the average frequency of the incoming data is less than the in Receive Multiplex mode, the signaling codeword (ABCD) are clocked average frequency of the RSCCK, the write pointer will be slower than out in the lower nibble of the timeslot with its corresponding data serializthe read pointer and the Elastic Store Buffer will be empty. The frame ing on the RSDn/MRSD[1:2] pins (as shown in the Figure - 5).
31
T1/J1-02AH) and IDLE (b2, T1/J1-02AH) are set to 1 respectively, the corresponding condition will cause an interrupt on the INT pin.
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
TS16 F0 0 0 0 0 X Y X X
Signaling Multi-Frame alignment pattern
RMAI Extra Bits
F1
A
B
C
D
A
B
C
D
to TS1
to TS17
F2
A
B
C
D
A
B
C
D
to TS2
to TS18
F15
A
B
C
D
A
B
C
D
to TS15
to TS31
Figure - 4. TS16 Arrangement in Signaling Multi-Frame
When the COSS (b6, E1-064H) is logic 1, all the COSS[30:1] (b5~0, E1-064H and b7~0, E1-065H and b7~0, E1-066H and b7~0, E1-067H) in the Receive CAS/RBS Buffer registers will reflect the change of the signaling of each timeslot respectively (excluding the TS0 and TS16). When the COSS (b6, E1-064H) is logic 0, the Receive CAS/RBS Buffer indirect registers (from 01H to 5FH of RCRB indirect registers) can be accessed by the microprocessor. The address of the indirect register is specified by the A[6:0] (b6~0, E1-066H). Whether the data are read from or written into the specified indirect register is determined by the R/WB (b7, E1-066H) and the data are in the D[7:0] (b7~0, E1-067H). The indirect registers have a read/write cycle. Before the read/write operation is completed, the BUSY (b7, E1-065H) will be set. New operations on the indirect registers can only be implemented when the BUSY (b7, E1-065H) is cleared. The read/write cycle is 490ns. The indirect registers are divided into three segments: two segments (from 01H to 1FH & from 21H to 3FH) contain the signaling bits of each timeslot; another segment (from 40H to 5FH) contains the signaling debounce configuration of each timeslot. A three-Signaling-Multi-Frame capacity buffer is used for signaling debounce and signaling freezing. Signaling debounce can be set by the DEB (b0, E1-RCRB-indirect registers - 41~5FH) which is activated by the PCCE (b0, E1-064H). It updates the signaling bits only when 2 consecutive signaling of a timeslot are the same. Signaling freeze will remain the signaling automatically when it is out of Signaling Multi-Frame synchronization or in unframed mode. The signaling bits are extracted to the A, B, C, D (b3~0, E1-RCRBindirect registers - 01~1FH or b3~0, E1-RCRB-indirect registers 21~3FH). There is a maximum 2 ms delay between the transition of the COSS[n] (E1-064H and E1-065H and E1-066H and E1-067H) and the
TS15 TS16 TS17 TS31 TS0
TS31
TS0
TS1
RSDn/ 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 MRSD[1:2] RSSIGn/ MRSSIG[1:2] ABCD ABCD
1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78
1 2 3 4 5 6 781 2 3 4 5 6 78
ABCD
ABCD
ABCD
Figure - 5. Signaling Output in E1 Mode
Channel 24 RSDn/ MRSD[1:2] RSSIGn/ MRSSIG[1:2]
Channel 1
Channel 2
Channel 24
Channel 1
12 3 45 67 8 F1 23 45 67 812 34 56 78
12345678F12345678
ABCD
ABCD
ABCD
ABCD
ABCD
F-bit or Parity
F-bit or Parity
Figure - 6. Signaling Output in T1 / J1 Mode
32
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
updating of the A, B, C, D code in the corresponding indirect registers (b3~0, E1-RCRB-indirect registers - 21~3FH). To avoid this 2 ms delay, users can read the corresponding b3~0 in the E1-RCRB-indirect registers - (01~1FH) first. If the value of these four bits are different from the previous A, B, C, D code, then the content of b3~0 in the E1-RCRB-indirect registers - (01~1FH) is the updated A, B, C, D code. If the content of the four bits is the same as the previous A, B, C, D code, then users should read the b3~0 in the E1-RCRB-indirect registers - (21~3FH) to get the updated A, B, C, D code. Any one of the 30-timeslot's signaling change will cause an interrupt on the INT pin if the SIGE (b5, E1-064H) is set. 3.9.2 T1 / J1 MODE When the frame is synchronized, the signaling is located in the Bit 8 of Frame 6 (A bit) and Frame 12 (B bit) in SF format, and is located in the Bit 8 of Frame 6 (A bit), Frame 12 (B bit), Frame 18 (C bit) and Frame 24 (D bit) in ESF format (refer to Table-3 & 4). The SF/ESF signaling format is selected by the ESF (b2, T1/J1-040H). When the RSCKn/RSSIGn/MRSSIG[1:2] pins are used as the signaling output, i.e. in Receive Clock Slave External Signaling mode or in Receive Multiplex mode, the signaling codeword (AB or ABCD) are clocked out in the lower nibble of the channel with its corresponding data serializing on the RSDn/MRSD[1:2] pins (as shown in the Figure - 6). However, in SF format, the signaling C and D are the repitition of signaling A and B. When the COSS (b6, T1/J1-040H) bit is logic 1, all the COSS[24:1] (b7~0, T1/J1-041H and b7~0, T1/J1-042H and b7~0, T1/J1-043H) in the Receive CAS/RBS Buffer registers will reflect the change of the signaling of each channel respectively. When the COSS (b6, T1/J1-040H) bit is logic 0, the Receive CAS/ RBS Buffer indirect registers (from 01H to 58H of RCRB indirect registers) can be accessed by the microprocessor. The address of the indirect register is specified by the A[6:0] (b6~0, T1/J1-042H). Whether the data are read from or written into the specified indirect register is determined by the R/WB (b7, T1/J1-042H) and the data is in the D[7:0] (b7~0, T1/J1-043H). The indirect registers have a read/write cycle. Before the read/write operation is completed, the BUSY (b7, T1/J1-041H) will be set. New operations on the indirect registers can only be done when the BUSY (b7, T1/J1-041H) is cleared. The read/write cycle is 650ns. The indirect registers are devided into three segments: two segments (from 01H to 18H & from 21H to 38H) contain the signaling bits of each channel; another segment (from 41H to 58H) contains the signaling debounce configuration of each channel. A three-superframe capacity buffer is used for signaling debounce and signaling freezing. Signaling debounce can be set by the DEB (b0, T1/J1-RCRB-indirect registers - 41~58H) which is activated by the PCCE (b0, T1/J1-040H). It updates the signaling bits only when 2 consecutive SF/ESF signaling bits of a channel are the same. Signaling freeze will remain the signaling automatically when it is out of SF/ESF sync or in unframed mode. The signaling bits are extracted to the A, B, C, D (b3~0, T1/J1RCRB-indirect registers - 01~18H or b3~0, T1/J1-RCRB-indirect registers - 21~38H). There is a maximum 2 ms delay between the transition of the COSS[n] (T1/J1-041H and T1/J1-042H and T1/J1-043H) and the updating of the A, B, C, D code in the corresponding indirect registers (b3~0,
T1/J1-RCRB-indirect registers - 21~38H). To avoid this 2 ms delay, users can read the corresponding b3~0 in the T1/J1-RCRB-indirect registers - (01~18H) first. If the value of these four bits are different from the previous A, B, C, D code, then the content of b3~0 in the T1/J1-RCRBindirect registers - (01~18H) is the updated A, B, C, D code. If the content of the four bits is the same as the previous A, B, C, D code, then users should read the b3~0 in the T1/J1-RCRB-indirect registers (21~38H) to get the updated A, B, C, D code. Any one of the 24-channel's signaling change will cause an interrupt on the INT pin if the SIGE (b5, T1/J1-040H) is set.
3.10 RECEIVE PAYLOAD CONTROL (RPLC)
Different test patterns can be inserted in the received data stream or the received data stream can be extracted to the PRBS Generator/Detector for test in this block. The Receive Payload Control of each framer operates independently. 3.10.1 E1 MODE To enable the test for the received data stream, the PCCE (b0, E105CH) must be set to activate the setting in the indirect registers (from 20H to 7FH of RPLC indirect registers). The following methods can be executed for test on a per-TS basis: - Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the received data of one of the eight framers will be extracted to the PRBS Generator/Detector when the RXPATGEN (b2, E1-00CH) is 0. The received data can be extracted in framed or unframed mode. The selection is made by the UNF_DET (b0, E1-00CH). In unframed mode, all the 32 timeslots are extracted and the per-timeslot configuration in the TEST (b7, E1-RPLCindirect registers - 20~3FH) is ignored. In framed mode, the received data will only be extracted on the timeslot configured by the TEST (b7, E1-RPLC-indirect registers - 20~3FH). Refer to the section of PRBS GENERATOR / DETECTOR (PRGD) for details. - Replace the data that will be output on the RSDn/MRSD pin with the value in the DTRK[7:0] (b7~0, E1-RPLC-indirect registers - 40~5FH) when the DTRKC/NxTS (b6, E1-RPLC-indirect registers - 20~3FH) of the corresponding timeslot is logic 1. (When it is out of Basic Frame synchronization, the value in the DTRK[7:0] [b7~0, E1-RPLC-indirect registers 40~5FH] can replace the data automatically if the AUTOOOF [b1, E1000H] is set. Or, when it is out of Basic Frame synchronization for 100ms, the value in the DTRK[7:0] [b7~0, E1-RPLC-indirect registers 40~5FH] can replace the data automatically if the AUTORED (b2, 000H) is set. These two kinds of data replacements can be executed even if the PCCE [b0, E1-05CH] is disabled and they replace all the timeslots.) - Replace the data that will be output on the RSDn/MRSD pin with the -law or A-law milliwatt pattern when the DMW (b4, E1-RPLC-indirect register - 20~3FH) of the corresponding timeslot is logic 1. (The milliwatt pattern is selectable between A-law and -law by the DMWALAW [b3, E1-RPLC-indirect register - 20~3FH]. Refer to Table - 8 & Table - 9.) - Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the test pattern from the PRBS Generator/Detector will replace the received data of one of the eight framers when the RXPATGEN (b2, E1-00CH) is 1. The test pattern can replace the received data in framed or unframed mode. The selection is made by the UNF_GEN (b1, E1-00CH). In unframed mode, all 32 timeslots are replaced and the per-timeslot configuration in the TEST (b7, E1-RPLC-indirect registers - 20~3FH) is ignored. In framed mode, the received data will only replace the timeslot configured by the TEST (b7, E1-RPLC-indirect registers - 20~3FH). Refer to the section of
33
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 8. A-Law Digital Milliwatt Pattern Bit 0 0 0 0 0 1 1 1 1 Bit 1 0 0 0 0 0 0 0 0 Bit 2 1 1 1 1 1 1 1 1 Bit 3 1 0 0 1 1 0 0 1 Bit 4 0 0 0 0 0 0 0 0 Bit 5 1 0 0 1 1 0 0 1 Bit 6 0 0 0 0 0 0 0 0 Bit 7 0 1 1 0 0 1 1 0
Table - 9. u-Law Digital Milliwatt Pattern Bit 0 Bit 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 Bit 2 0 0 0 0 0 0 0 0 Bit 3 1 0 0 1 1 0 0 1 Bit 4 1 1 1 1 1 1 1 1 Bit 5 1 0 0 1 1 0 0 1 Bit 6 1 1 1 1 1 1 1 1 Bit 7 0 1 1 0 0 1 1 0
PRBS GENERATOR / DETECTOR (PRGD) for details. - Invert the most significant bit, the even bits and/or odd bits that will be output on the RSDn pin when the SIGNINV and the RINV[1:0] (b2~0, E1-RPLC-indirect registers - 20~3FH) of the corresponding timeslot is set. (The above methods are arranged from highest to lowest in priority.) - Replace the signaling that will be output on the RSSIGn pin with the value in the A, B, C, D (b3~0, E1-RPLC-indirect registers - 61~7FH) when the STRKC (b5, E1-RPLC-indirect registers - 20~3FH) of the corresponding timeslot allows. The data and signaling of all timeslots can be replaced with the setting in the DTRK[7:0] (b7~0, E1-RPLC-indirect registers - 40~5FH) and the A, B, C, D (b3~0, E1-RPLC-indirect registers - 61~7FH) respectively when the RXMTKC (b0, E1-001H) is set. To enable this function, PCCE (b0, E1-05CH) must be set to 1. Addressed by the A[6:0] (b6~0, E1-05EH), the data read from or written into the indirect registers are in the D[7:0] (b7~0, E1-05FH). The read or write operation is determined by the R/WB (b7, E1-05EH). The indirect registers have a read/write cycle. Before the read/write operation is completed, the BUSY (b7, E1-05DH) will be set. New operations on the indirect registers can only be implemented when the BUSY (b7, E105DH) is cleared. The read/write cycle is 490ns. 3.10.2 T1 / J1 MODE To enable the test for the received data stream, the PCCE (b0, T1/ J1-050H) must be set to activate the setting in the indirect registers (from 01H to 48H). The following methods can be used for test on a perchannel basis: - Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the received data of one of the eight framers will be extracted to the PRBS Generator/Detector when the RXPATGEN (b2, T1/J1-00FH) is 0. The received data can be extracted in framed or unframed mode. The selection is made by the UNF_DET (b0, T1/J1-00FH). In unframed mode, all the 24 channels and the F-bit are extracted and the per-channel configuration in the TEST (b3, T1/J1-RPLC-indirect registers - 01~18H) is ignored. In framed mode, the received data will only be extracted on the channel specified by the TEST (b3, T1/J1-RPLC-indirect registers - 01~18H). Fractional T1/J1 signal can also be extracted in the specified channel when the Nx56k_DET (b3, T1/J1-00FH) is set. Refer to the section of PRBS GENERATOR / DETECTOR (PRGD) for details. - Replace the data that will be output on the RSDn/MRSD pin with the value in the DTRK[7:0] (b7~0, T1/J1-RPLC-indirect registers 34
19~30H) when the DTRKC (b6, T1/J1-RPLC-indirect registers - 01~18H) of the corresponding channel is logic 1. (When it is out of SF/ESF synchronization, the value in the DTRK[7:0] (b7~0, T1/J1-RPLC-indirect registers - 19~30H) can replace the data automatically if the AUTOOOF (b1, T1/J1-000H) is set. Or, when the RED alarm is declared, the value in the DTRK[7:0] (b7~0, T1/J1-RPLC-indirect registers - 19~30H) can replace the data automatically if the AUTORED (b2, T1/J1-000H) is set. These two kinds of data replacements can be executed even if the PCCE (b0, T1/J1-050H) is disabled and they replace all the channels.) - Replace the data that will be output on the RSDn/MRSD pin with the milliwatt pattern when the DMW (b5, T1/J1-RPLC-indirect register 01~18H) of the corresponding channel allows. (The milliwatt is -law. Refer to Table - 9.) - Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the test pattern from the PRBS Generator/Detector will replace the received data of one of the eight framers when the RXPATGEN (b2, T1/J1-00FH) is 1. The test pattern can replace the received data in framed or unframed mode. The selection is made by the UNF_GEN (b1, T1/J1-00FH). In unframed mode, all the 24 channels and the F-bit are replaced and the per-channel configuration in the TEST (b3, T1/J1-RPLC-indirect registers - 01~18H) is ignored. In framed mode, the received data will only be replaced on the channel specified by the TEST (b3, T1/J1-RPLC-indirect registers - 01~18H). Fractional T1/J1 signal can also be replaced in the specified channel when the Nx56k_GEN (b4, T1/J1-00FH) is set. Refer to the section of PRBS GENERATOR / DETECTOR (PRGD) for details. - Invert the most significant bit and/or the other bits in a channel that will be output on the RSDn/MRSD pin when the SIGNINV and the INVERT (b4 & b7, T1/J1-RPLC-indirect registers - 01~18H) of the corresponding channel are set. - Fix the signaling bit with the value in the POL (b0, T1/J1-RPLC-indirect registers - 01~18H) when the FIX (b1, T1/J1-RPLC-indirect registers - 01~18H) of the corresponding channel is logic 1. (The above methods are arranged from highest to lowest in priority.) - Replace the signaling that will be output on the RSSIGn/MRSSIG pin with the value in the A, B, C, D (b3~0, T1/J1-RPLC-indirect registers 31~48H) when the STRKC (b7, T1/J1-RPLC-indirect registers - 31~48H) of the corresponding channel is logic 1. The data and signaling of all channels can be replaced with the setting in the DTRK[7:0] (b7~0, T1/J1-RPLC-indirect registers - 19~30H) and the A, B, C, D (b3~0, T1/J1-RPLC-indirect registers - 31~48H) respectively when the IMTKC (b0, T1/J1-001H) is set. To enable this function, the PCCE (b0, T1/J1-050H) must be set to 1.
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Addressed by the A[6:0] (b6~0, T1/J1-052H), the data read from or written into the indirect registers are in the D[7:0] (b7~0, T1/J1-053H). The read or write operation is determined by the R/WB (b7, T1/J1052H). Before the read/write operation is completed, the BUSY (b7, T1/ J1-051H) will be set. New operations on the indirect registers can only be implemented when the BUSY (b7, T1/J1-051H) is cleared. The read/ write cycle is 650ns.
3.11 RECEIVE SYSTEM INTERFACE (RESI)
The Receive System Interface determines how to output the received data to the system back-plane. The data from the eight framers can be aligned with each other or be output independently. The timing clocks and framing pulses can be provided by the system back-plane common to eight framers, or obtained from the far end of the individual eight framers. The Receive System Interface supports various configurations to meet various requirements in different applications. 3.11.1 E1 MODE In E1 mode, the Receive System Interface can be set in Nonmultiplexed Mode or Multiplexed Mode. In Non-multiplexed Mode, the RSDn pin is used to output the received data from each framer at the bit rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data from the eight framers are byte interleaved to form two high speed data streams and output on the MRSD1 and MRSD2 pins at the bit rate of 8.192 Mb/s.
In the Non-multiplexed Mode, if the timing signal for clocking data on RSDn pin is provided by the system side and shared by all eight framers, the Receive System Interface should be set in Receive Clock Slave mode. If the timing signal for clocking data on each RSDn pin is received from each line side, the Receive System Interface should be set in Receive Clock Master mode. In the Receive Clock Slave mode, if the multi-function pin RSCKn/ RSSIGn is used to output a reference clock, the Receive System Interface is in Receive Clock Slave RSCK Reference Mode. If the RSCKn/RSSIGn pin is used to output the extracted signaling bits, the Receive System Interface is in Receive Clock Slave External Signaling mode. In the Receive Clock Master mode, if the data in all 32 timeslots in an E1 basic frame is clocked out by the RSCKn, the Receive System Interface is in Receive Clock Master Full E1 mode. If the data in only some of the timeslots in an E1 frame are clocked out by the RSCKn, then the Receive System Interface is in Receive Clock Master Fractional E1 (with F-bit) Mode. Table - 10 summarizes the receive system interface in different operation modes. To set the receive system interface of each framer into various operation modes, the registers must be configured as Table - 11.
Table - 10. E1 Mode Receive System Interface in Different Operation Modes Operation Mode NonClock Slave Multiplexed Mode Mode Clock Master Mode Multiplexed Mode
Note:
RSCK Reference External Signaling Full E1 Fractional E1 (with F-bit)
Data Pin RSDn RSDn RSDn RSDn MRSD
Clock Pin RSCCK RSCCK RSCKn RSCKn MRSCCK
Framing Pin Signaling Pin Reference Clock RSCFS & RSFSn * No RSCKn RSCFS & RSFSn * RSSIGn No RSFSn No No RSFSn No No MRSCFS & MRSFS * MRSSIG No
* In Receive Clock Slave mode and Receive Multiplexed mode, there are two framing signals. In Receive Clock Slave mode, the framing pulses on RSCFS can be ignored for some framers by setting the FPMODE (b5, E1-011H) to 0. However, in Receive Multiplexed mode, when the FPMODE (b5, E1-011H) of any of the eight framers is configured as logic 1, all the others are taken as logic 1. Only when all the FPMODE (b5, E1-011H) of the eight framers are configured as logic 0, the frame pulses on MRSCFS can be ignored. That is, the FPMODE (b5, E1-011H) should be configured to the same value in Receive Multiplexed mode. Table - 11. Operation Mode Selection in E1 Receive Path
RATE[1:0] (b1~0, E1-010H) 01 0 11 (All the eight framers should be set) 1 1 RSCKSLV (b5, E1-010H) 1 RSSIG_EN (b6, E1-001H) 0 1 FRACTN[1:0] (b7~6, E1-010H) 00 10 11 -
Operation Mode Receive Clock Slave RSCK Reference Receive Clock Slave External Signaling Receive Clock Master Full E1 Receive Clock Master Fractional E1 Receive Clock Master Fractional E1 with F-bit Receive Multiplexed
35
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.11.1.1 Receive Clock Slave Mode In the Receive Clock Slave Mode, the Receive Side System Common Clock (RSCCK) is provided by the system side. It is used as a common timing clock for all eight framers. The speed of the RSCCK can be selected by the CMS (b2, E1-010H) to be the same as the received data (2.048MHz), or double of the received data (4.096 MHz). The CMS (b2, E1-010H) of the eight framers should be set to the same value. If the speed of the RSCCK is double that of the received data stream, there will be two active edges in one bit duration. In this case, the RSD_RSCFS_EDGE (b5, E1-014H) determines the active edge to update the signal on the RSDn, RSSIGn and RSFSn pins; however, the pulse on the RSCFS (if exists) is always samples on its first active edge. In the Receive Clock Slave Mode, the Receive Side System Common Frame Pulse (RSCFS) is used as a common framing signal to align the data streams for all eight framers. The RSCFS asserts on each Basic Frame and its valid polarity is configured by the FPINV (b6, E1-011H). The framing signals on RSCFS can also be ignored by setting the FPMODE (b5, E1-011H) to 0. In the Receive Clock Slave Mode, the bit rate on the RSDn pin is 2.048Mb/s. In the Receive Clock Slave Mode, the Receive Side System Frame Pulse (RSFSn) can be configured by the PERTS_RSFS (b3, E1-00EH) and REF_MRSFS (b2, E1-00EH) to output all zeros, to indicate the frame position or to output the same pulse as the RSCFS. When it is defined to indicate the frame position, it can indicate the first bit of a Basic Frame, Signaling Multi-frame, CRC-Multiframe, or both the Signaling and CRC-multiframe. This selection is made by the ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H). When the RSFSn is for framing pulse indication, the valid polarity of it is configured by the FPINV (b6, E1-011H). In this case, if the FPMODE (b5, E1-011H) is low, the RSFSn can only indicate the Basic Frame no matter what the setting in the ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H). The Receive Clock Slave Mode includes two sub-modes: Receive Clock Slave RSCK Reference Mode and Receive Clock Slave External Signaling Mode.
3.11.1.1.1 Receive Clock Slave RSCK Reference Mode In this mode (refer to Figure - 7), the data on the system interface is clocked by the RSCCK. The active edge of the RSCCK to sample the pulse on the RSCFS or to update the data on the RSDn and RSFSn pins is determined by the following bits in the registers (refer to Table 12). Table - 12. Active Edge Selection of RSCCK (in E1 Receive Clock Slave RSCK Reference Mode)
Bit Determining the Active Edge of the RSCCK RSCFS RSFSn RSDn FE (b3, E1-010H) DE (b4, E1-010H)
Note: If the setting of the FE (b3, E1-010H) and DE (b4, E1-010H) is different, the RSFSn will be one clock edge ahead of RSDn. The FE (b3, E1-010H) of the eight framers should be set to the same value to ensure the RSCFS for the eight framers is sampled on the same active edge. Note: There is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is equal to FE (b3, E1-010H). The RSD_RSCFS_EDGE (b5, E1-014H) is invalid and the signal on the RSDn and the RSFSn pins are updated on the first active edge of RSCCK.
Figure - 8 & 9 show the functional timing examples. Bit 1 of each timeslot is the first bit to be output. Besides all the common functions described in the Receive Clock Slave mode, the special feature in this mode is that the multi-functional pin RSCKn/RSSIGn is used as RSCKn to output a reference clock. The RSCKn can be selected by the RSCKSEL (b5, E1-001H) to output a jitter attenuated 2.048MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed LRCKn divided by 256).
RSCCK RSCFS * Elastic Store
Frame Processor Receive System Interface
FIFO DPLL
LRD[1:8] LRCK[1:8]
RSD[1:8] * RSFS[1:8] * RSCK[1:8]
Divider 8kHz RECEIVER
Note: * RSCFS, RSD, RSFS are timed to RSCCK
Figure - 7. Receive Clock Slave RSCK Reference Mode
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b2, E1-010H) is logic 0, i.e., the backplane clock rate is 2.048Mbit/s. The DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0. The timeslot offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 TS31 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6
(The RSCKn is selected by the RSCKSEL (b5, E1-001H) to output a jitter attenuated 2.048MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed LRCKn divided by 256).)
Figure - 8. E1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 1
The CMS (b2, E1-010H) is logic 1, i.e., the backplane clock rate is 4.096Mbit/s. The DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 1. RSCFS RSCCK RSFSn When the RSD_RSCFS_EDGE (b5, E1-014H) is logic 1: RSDn 1 2 3 4 5 TS31 When the RSD_RSCFS_EDGE (b5, E1-014H) is logic 0: RSDn 1 2 3 4 5 TS31 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6
(The RSCKn is selected by the RSCKSEL (b5, E1-001H) to output a jitter attenuated 2.048MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed LRCKn divided by 256).)
Figure - 9. E1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 2
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.11.1.1.2 Receive Clock Slave External Signaling Mode In this mode (refer to Figure - 10), the data on the system interface is clocked by the RSCCK. The active edge of the RSCCK used to sample the pulse on the RSCFS or to update the data on the RSDn, RSFSn and RSSIGn is determined by the following bits in the registers (refer to Table - 13). Figure - 11 & 12 show the functional timing examples. Bit 1 of each timeslot is the first bit to be output. Besides all the common functions described in the Receive Clock Slave mode, the special feature in this mode is that the multi-functional pin RSCKn/RSSIGn is used as RSSIGn to output the extracted signaling bits. The extracted signaling bits are timeslot aligned with the data on the RSDn pin (refer to Figure - 5). In the Out of Signaling Multi-Frame condition, the output signaling bits ABCD on the RSSIGn pin can be forced to be all ones if the OOSMFAIS (b2, E1-001H) is set to 1.
Table - 13. Active Edge Selection of RSCCK (in E1 Receive Clock Slave External Signaling Mode)
Bit Determining the Active Edge of the RSCCK RSCFS RSFSn RSDn RSSIGn FE (b3, E1-010H) DE (b4, E1-010H)
Note: If the setting of the FE (b3, E1-010H) and DE (b4, E1-010H) is different, the RSFSn will be one clock edge ahead of RSDn. The FE (b3, E1-010H) of the eight framers should be set to the same value to ensure the RSCFS for the eight framers is sampled on the same active edge. There is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is equal to FE (b3, E1-010H). The RSD_RSCFS_EDGE (b5, E1-014H) is invalid and the signal on the RSDn, RSSIGn and RSFSn pins are updated on the first active edge of RSCCK.
RSCCK RSCFS * FIFO DPLL RECEIVER LRD[1:8] LRCK[1:8]
RSD[1:8] * RSFS[1:8] * RSSIG[1:8] *
Receive System Interface
Frame Processor Elastic Store
Note: * RSCFS, RSD, RSSIG, RSFS are timed to RSCCK
Figure - 10. Receive Clock Slave External Signaling Mode
The CMS (b2, E1-010H) is logic 0, i.e., the bankplane rate is 2.048Mbit/s. The DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 0. The timeslot offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn 1 2 3 4 5 TS31 RSSIGn X X X X A B C D P X X X 6 7 8 1 2 3 4 5 TS0 X X X X X X X 6 7 8 1 2 3 4 TS1 X A B 5 6
RSDn
(The 'X' represents the filled bits and has no meaning. The 'P' represents the Parity bit..)
Figure - 11. E1 Receive Clock Slave External Signaling Mode - Functional Timing Example 1
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b2, E1-010H) is logic 1, i.e., the bankplane rate is 4.096Mbit/s. The DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 1. * The timeslot offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn 1 2 3 4 5 TS31 RSSIGn X X X X A B C D P X X X 6 7 8 1 2 3 4 5 TS0 X X X X X X X 6 7 8 1 2 3 4 TS1 X A B 5 6
RSDn
(The 'X' represent the filled bits and has no meaning. The 'P' represents the Parity bit..) Note: * It is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is equal to FE (b3, E1-010H). The signal on the RSDn, RSSIGn and RSFSn are updated on the first active edge of RSCCK.
Figure - 12. E1 Receive Clock Slave External Signaling Mode - Functional Timing Example 2 3.11.1.2 Receive Clock Master Mode In the Receive Clock Master mode, each framer uses its own clock signal on RSCKn pin and framing signal on RSFSn pin to output the data on each RSDn pin. As the common framing signal RSCFS is not used, the FPMODE bit (b5, E1-011H) must be set to 0. In the Receive Clock Master Mode, the bit rate on the RSDn pin is 2.048Mb/s. In the Receive Clock Master Mode, the RSFSn can be configured by the PERTS_RSFS (b3, E1-00EH) and REF_MRSFS (b2, E1-00EH) to output all zeros, to indicate the frame position or to output the same pulse as the RSCFS. When it is defined to indicate the frame position, it can indicate the first bit of a Basic Frame, Signaling Multi-frame, CRCMultiframe, or both the Signaling and CRC-multiframe. This selection is made by the ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H). When the RSFSn is used for framing pulse indication, the valid polarity of it is configured by the FPINV (b6, E1-011H). In this case, if the FPMODE (b5, E1-011H) is low, the RSFSn can only indicate the Basic Frame no matter what the setting in the ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H). In the Receive Clock Master Mode, the data on the system interface is clocked by the RSCKn. The active edge of the RSCKn used to update the data on the RSDn and RSFSn is determined by the DE (b4, E1010H) and the FE (b3, E1-010H) respectively as shown in Table - 14. The Receive Clock Master Mode includes two sub-modes: Receive Clock Master Full E1 Mode and Receive Clock Master Fractional E1 (with F-bit) Mode. Table - 14. Active Edge Selection of RSCK (in E1 Receive Clock Master Mode)
the Bit Determining the Active Edge of the RSCKn FE (b3, E1-010H) DE (b4, E1-010H)
RSFSn RSDn
Note: If the setting in the FE (b3, E1-010H) and DE (b4, E1-010H) is different, the RSFSn will be one clock edge ahead of RSDn.
3.11.1.2.1 Receive Clock Master Full E1 Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode (refer to Figure - 13) is that the RSCKn is a standard 2.048MHz clock, and the data in all 32 timeslots in a standard E1 frame is clocked out by the RSCKn. Figure - 14 shows the functional timing examples. Bit 1 of each timeslot is the first bit to be output.
39
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
RSD[1:8] * RSFS[1:8] *
Receive System Interface
Frame Processor
FIFO DPLL RECEIVER
LRD[1:8] LRCK[1:8]
RSCK[1:8] Note: * RSD, RSFS are timed to RSCK
Figure - 13. Receive Clock Master Full E1 or T1/J1 Mode
RSCK is 2.048M: RSCKn When the DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0: RSFSn RSDn
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When the DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 1: RSFSn RSDn
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When the DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 1: RSFSn 1 2 3 4 5 TS31 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6
RSDn
Figure - 14. E1 Receive Clock Master Full E1 Mode - Functional Timing Example
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.11.1.2.2 Receive Clock Master Fractional E1 (with F-bit) Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode (refer to Figure - 15) is that the RSCKn is a gapped 2.048MHz clock (no clock signal during the selected timeslot). In the Receive Clock Master Fractional E1 mode, the RSCKn is gapped during those timeslots with their DTRKC/NxTS (b6, E1-RPLC-indirect register - 20~3FH) in Receive Payload Control are logic 1. It clocks out during those timeslots with their DTRKC/NxTS_IDLE (b6, E1RPLC-indirect register - 20~3FH) set to logic 0. The data in the corresponding gapped timeslot is a don't-care. Figure - 16 shows the functional timing examples. Bit 1 of each timeslot is the first bit to be output. The Receive Clock Master Fractional E1 with F-bit mode supports ITU recommendation G.802 where an E1 clock is output as a 193-bit T1 clock. In this mode, the RSCKn that starts from the 2nd bit of TS26 and ends at the last bit of the same Basic Frame are gapped, and the TS16 is also gapped. Thus, the DTRKC/NxTS (b6, E1-RPLC-indirect register 20~3FH) of the timeslots of which the clock are gapped are invalid. The gapping of the remaining timeslots is still determined by the DTRKC/ NxTS (b6, E1-RPLC-indirect register - 20~3FH), and the data in the corresponding gapped timeslot is a don't-care. 3.11.1.3 Receive Multiplexed Mode In this mode (refer to Figure - 17), two multiplexed buses are used to receive the data from all eight framers. The data from up to four framers is byte-interleaved and output on one of the two multiplexed buses. The multiplexed bus is selected by the MRBS (b4, E1-001H). When the data from four framers are output on one multiplexed bus, the sequence of data is arranged by setting the timeslot offset TSOFF[6:0] (b6~0, E1013H). The data from different framers on one multiplexed bus must be shifted by a different timeslot offset to avoid data mixing. Then the received data of each framer can be controlled by the MRBC (b3, E1001H) to output to the selected multiplexed bus or not. In the Receive Multiplexed mode, the data on the system interface are clocked by the MRSCCK. The active edge of the MRSCCK to sample the pulse on the MRSCFS and to update the data on the MRSD, MRSFS and MRSSIG are determined by the following bits in the registers (refer to Table - 15). In the Receive Multiplexed mode, the Multiplexed Receive Side System Common Clock (MRSCCK) is provided by the system side. It is used as a common timing clock for all eight framers. The frequency of the RSCCK can be selected by the CMS (b2, E1-010H) to be the same as the bit rate of the received data stream (8.192Mb/s), or double the
Table - 15. Active Edge Selection of MRSCCK (in E1 Receive Multiplexed Mode)
Bit Determining the Active Edge of the MRSCCK MRSCFS MRSFS MRSD MRSSIG FE (b3, E1-010H) DE (b4, E1-010H)
Note: if the setting in the FE (b3, E1-010H) and DE (b4, E1-010H) is different, the MRSFS will be one clock edge ahead of MRSD. The FE (b3, E1-010H) and DE (b4, E1-010H) of all eight framers should be configured to the same value. There is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is equal to FE (b3, E1-010H). The RSD_RSCFS_EDGE (b5, E1-014H) is invalid and the signal on the MRSD, MRSSIG and MRSFS pins are updated on the first active edge of MRSCCK.
bit rate of the received data stream (16.384 Mb/s). If the frequency of the RSCCK is double the bit rate of the received data stream, there will be two active edges in one bit time. In this case, the RSD_RSCFS_EDGE (b5, E1-014H) determines the active edge to update the signal on the MRSD, MRSSIG and MRSFS pin; however, the pulse on the MRSCFS (if it exists) is always samples on its first active edge. However, if the CMS (b2, E1-010H) or the RSD_RSCFS_EDGE (b5, E1-014H) of any of the eight framers is configured as logic 1, all the others are taken as logic 1. That is, the CMS (b2, E1-010H) and the RSD_RSCFS_EDGE (b5, E1-014H) of the eight framers should be configured to the same value in the Receive Multiplexed mode. In the Receive Multiplexed mode, the Multiplexed Receive Side System Common Frame Pulse (MRSCFS) is used as a common framing signal to align the data streams on the two multiplexed buses. The MRSCFS asserts on each first bit of Basic Frame of the selected first framer. The valid polarity of the MRSCFS is configured by the FPINV (b6, E1-011H). The framing signals on MRSCFS can also be ignored by setting the FPMODE (b5, E1-011H) to 0. The FPINV (b6, E1011H) and the FPMODE (b5, E1-011H) of the eight framers should be set to the same value. In the Receive Multiplexed mode, the bit rate on the MRSD pin is 8.192Mb/s. In the Receive Multiplexed mode, the MRSFS can be configured by the PERTS_RSFS (b3, E1-00EH) and REF_MRSFS (b2, E1-00EH) to output all zeros, to indicate the frame position or to output the same
RSD[1:8] * RSFS[1:8] *
Receive System Interface
Frame Processor
FIFO DPLL RECEIVER
LRD[1:8] LRCK[1:8]
RSCK[1:8] Note: * RSD, RSFS are timed to gapped RSCK
Figure - 15. Receive Clock Master Fractional E1 or T1/J1 Mode
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
RSCK is 2.048M. In this example, RSCK is supposed to be held in an inactive state during TS0. When the DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0: RSCKn RSFSn RSDn
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5 TS31
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Don't Care
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When the DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 0: RSCKn RSFSn RSDn
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When the DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 1: RSCKn RSFSn RSDn
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When the DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 1: RSCKn RSFSn RSDn
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Figure - 16. E1 Receive Clock Master Fractional E1 Mode - Functional Timing Example
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
MRSCCK MRSCFS * MRSD[1:2] * MRSFS[1:2] * MRSSIG[1:2] * Receive System Interface
The Other Four of the Framer #1~#8 FIFO Frame Any Four of the Framer #1~#8 Processor DPLL FIFO Frame DPLLFIFO Processor Frame DPLL Processor DPLL Elastic Store
LRD[1:8] LRCK[1:8]
Note: * MRSCFS, MRSD, MRSFS, MRSSIG are timed to MRSCCK
Figure - 17. Receive Multiplexed Mode pulse as the MRSCFS. The PERTS_RSFS (b3, E1-00EH) and REF_MRSFS (b2, E1-00EH) of the eight framers should be set to the same value. When it is defined to indicate the frame position, it can only indicate the first bit of a Basic Frame of the selected first framer no matter what is set in the ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H). When the MRSFS is for framing pulse indication, the valid polarity of it is configured by the FPINV (b6, E1-011H). The FPINV (b6, E1-011H) of the eight framers should be set to the same value. In the Receive Multiplexed mode, the MRSSIG outputs extracted signaling. The extracted signaling bits are timeslot aligned with the data outputted on the MRSD. In the Out of Signaling Multi-Frame condition, the output signaling ABCD on the MRSSIG pin can be forced to be all ones if the OOSMFAIS (b2, E1-001H) is set. Figure - 18 & 19 show the functional timing examples. Bit 1 of each timeslot is the first bit to be output. 3.11.1.4 Parity Check & Polarity Fix In all the above modes except for the Receive Clock Slave Fractional E1 (with F-bit) mode, if the RPTYE (b6, E1-012H) is logic 1, parity check can be conducted over the bits in the previous Basic Frame and the result is inserted into the first bit (MSB) of TS0 on RSDn/MRSD pin. The even parity or odd parity is selected by the RPTYP (b7, E1-012H) and
The CMS (b2, E1-010H) is logic 0, i.e., the bankplane rate is 8.192Mbit/s. The DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 0. In this example, Framer1 to Framer4 are supposed to be multiplexed to one multiplexed bus. MRSCFS
MRSCCK When the TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF_EN of the four Framers are set to logic 0: MRSFS
MRSD
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Framer1_TS0 MRSSIG C D X X X X A B C D X X X
Framer2_TS0 X A B C D X X X
Framer3_TS0 X A B C D X X X
Framer4_TS0 X A B C DX X X X
Framer1_TS1 A B C D
(The 'X' represent the filled bits and has no meaning.)
Figure - 18. E1 Receive Multiplexed Mode - Functional Timing Example 1
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
The CMS (b2, E1-010H) is logic 1, i.e., the bankplane rate is 16.384Mbit/s. The DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0. In this example, Framer1 to Framer4 are supposed to be multiplexed to one multiplexed bus. MRSCFS MRSCCK
INDUSTRIAL TEMPERATURE RANGES
When the TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF_EN of the four Framers are set to logic 0: MRSFS
MRSD
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Framer1_TS0 MRSSIG C D X X X X A B C D X X
Framer2_TS0 X X A B C D X X
Framer3_TS0 X X A B C D X X
Framer4_TS0 X X A B C D X X X
Framer1_TS1 X A B C D
(The 'X' represent the filled bits and has no meaning.)
Figure - 19. E1 Receive Multiplexed Mode - Functional Timing Example 2 whether the first bit of TS0 is calculated or not is determined by the PTY_EXTD (b3, E1-012H). Alternatively this first bit of TS0 can be forced to be logic 0 or 1 by setting the value in the FIXPOL (b4, E1012H), when the FIXF (b5, E1-012H) is set. The priority of the FIXF (b5, E1-012H) is lower than the RPTYE (b6, E1-012H). 3.11.1.5 Offset In the above five modes, timeslot offset and/or bit offset can be configured. If the offset is configured, the offset between different operation modes is summarized in Table - 16. Bit offset is disabled when the CMS (b2, E1-010H) is logic 1. The timeslot offset is configured in the TSOFF[6:0] (b6~0, E1-013H). The TSOFF[6:0] (b6~0, E1-013H) give a binary representation. Enabled by the BOFF_EN (b3, E1-014H), the bit offset is configured in the BOFF[2:0] (b2~0, E1-014H). The bit offset follows the Concentration Highway Interface (CHI) specification (refer to Table - 17 & 18). When the bit offset is between the RSCFS/MRSCFS and the start of the corresponding frame on the RSDn/MRSD, the CET (clock edge transmit) is counted from the active edge of the RSCFS/MRSCFS (refer to the example in Figure - 20). The pulse on the RSFSn/MRSFS and the signal on the RSSIGn/MRSSIG (if it exists) are aligned to the RSDn/ MRSD. When the bit offset is between the RSFSn/MRSFS and the start of the corresponding frame on the RSDn/MRSD, the CET is counted from the active edge of the RSFSn/MRSFS (refer to the example in Figure - 21). The signal on the RSSIGn/MRSSIG (if it exists) is aligned to the RSDn/MRSD. Note that it is a special case when the BRXSMFP and the ALTIFP (b2, b0, E1-011H) are both set to logical 1. In this case, there is bit offset between the output on the RSFSn and RSDn. Refer to Table - 19 for the details. 3.11.1.6 Output On RSDn/MRSD & RSSIGn/MRSSIG In all the five modes, the RSDn/MRSD and the RSSIGn/MRSSIG pin can be configured by the TRI[1:0] (b1~0, E1-012H) of the corresponding framer to be in high impedance state or to output the processed data stream. The data output on the RSDn/MRSSIG pin can also be forced to be all ones, and the signaling output on the RSSIGn/MRSSIG pin (if it exists) can be forced to be frozen at the current valid signaling when the RAIS (b1, E1-007H) is set.
44
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 16. Offset in Different Operation Modes
Operation Mode Receive Clock Slave mode 0 Receive Clock Master mode Receive Multiplexed mode 0 (must be zero) 1 (in any of the eight framers) 0 FPMODE (b5, E1-011H) 1 Offset The offset is between the RSCFS and the start of the corresponding frame on the RSDn (and RSSIGn). The offset is between the RSFSn and the start of the corresponding frame on the RSDn (and RSSIGn). The offset is between the RSFSn and the start of the corresponding frame on the RSDn. The offset is between the MRSCFS and the start of the corresponding frame on the MRSD and MRSSIG. The offset is between the MRSFS and the start of the corresponding frame on the MRSD and MRSSIG.
Table - 17. Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 0) FE DE (b3, E1-010H) (b4, E1-010H) 0 0 0 1 1 0 1 1 BOFF[2:0] (b2~0, E1-014H) 011 100 10 12 9 11 9 11 10 12
000 4 3 3 4
001 6 5 5 6
010 8 7 7 8
101 14 13 13 14
110 16 15 15 16
111 18 17 17 18
CET
Table - 18. Receive System Interface Bit Offset (FPMODE [b5, E1-011H] = 1) FE DE (b3, E1-010H) (b4, E1-010H) 0 0 0 1 1 0 1 1 BOFF[2:0] (b2~0, E1-014H) 011 100 8 10 7 9 7 9 8 10
000 2 1 1 2
001 4 3 3 4
010 6 5 5 6
101 12 11 11 12
110 14 13 13 14
111 16 15 15 16
CET
Table - 19. Bit Offset Between RSFSn and RSDn When the BRXSMFP and the ALTIFP (b2, b0, E1-011H) are Both Set To Logical 1
BOFF_EN (b3, E1-014H) 0 FPMODE (b5, E1-011H) X 1 1 0
DE (b4, E1-010H) & FE (b3, E1-010H) Same Difference Same Difference Same Difference
Bit Offset Between the RSFSn and the RSDn 1 bit offset. RSFSn is ahead. 1.5 bit offset. RSFSn is ahead. 1 bit offset. RSFSn is ahead. 1.5 bit offset. RSFSn is ahead. CHI specification (Table - 17)
45
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
For example: when DE (b4, E1-010H) = 0, FE (b3, E1-010H) = 0 starting edge (CET=0) 1 2 3 CET=4 RSCFS RSCCK The bit offset is 0: RSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
The bit offset is set as: BOFF_EN (b3, E1-014H) = 1, BOFF[2:0] (b2~0, E1-014H) = 000; i.e. the CET = 4: RSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
Figure - 20. Receive Bit Offset - Between RSCFS & RSDn
For example: when DE (b4, E1-010H) = 1, FE (b3, E1-010H) = 0 starting edge 1 2 CET=3 (CET=0) RSFSn RSCCK/RSCKn The bit offset is 0: RSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
The bit offset is set as: BOFF_EN (b3, E1-014H) = 1, BOFF[2:0] (b2~0, E1-014H) = 001; i.e. the CET = 3: RSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
Figure - 21. Receive Bit Offset - Between RSFSn & RSDn
46
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.11.2 T1 / J1 MODE In T1/J1 mode, the Receive System Interface can be set in Nonmultiplexed Mode or Multiplexed Mode. In Non-multiplexed Mode, the RSDn pin is used to output the received data from each framer at the bit rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed Mode, the received data from the eight framers are converted to 2.048 Mb/s format and byte interleaved to form two high speed data streams and output on the MRSD1 and MRSD2 pins at the bit rate of 8.192 Mb/s. In the Non-multiplexed Mode, if the timing signal for clocking data on the RSDn pin is provided by the system side and shared by all eight framers, the Receive System Interface should be set in Receive Clock Slave mode. If the timing signal for clocking data on each RSDn pin is received from each line side, the Receive System Interface should be set in Receive Clock Master mode. In the Receive Clock Slave mode, if the multi-function pin RSCKn/ RSSIGn is used to output a reference clock, the Receive System Interface is in Receive Clock Slave RSCK Reference Mode. If the RSCKn/RSSIGn pin is used to output the extracted signaling bits, the Receive System Interface is in Receive Clock Slave External Signaling mode. The T1/J1 mode E1 rate, which means the system clock rate is 2.048 MHz in T1/J1 mode, can only be supported in the Receive Clock Slave mode. In the Receive Clock Master mode, if the data in all 24 channels of a T1/J1 basic frame is clocked out by the RSCKn signal, the Receive System Interface is in Receive Clock Master Full T1/J1 mode. If the data in only some timeslots of a T1/J1 frame is clocked out by the RSCKn, then the Receive System Interface is in Receive Clock Master Fractional T1/J1 Mode.
Table - 20 summarizes the receive system interface in different operating modes. To set the receive system interface of each framer into various operating modes, the registers must be configured as Table - 21. 3.11.2.1 Receive Clock Slave Mode In the Receive Clock Slave Mode, the bit rate on the RSDn pin is 1.544Mb/s. However, if the system clock rate is 2.048MHz, the received data stream (1.544 Mb/s) should be converted to the same rate as the system side, that is, to work in T1/J1 mode E1 rate. Thus, the RSCCK2M (b4, T1/J1-001H) and the RSCCK8M (b3, T1/J1-001H) should be set to logic 1 and 0 respectiively. The conversion complies as follows: One dummy byte is inserted in the system side before 3 bytes of Frame N from the device are converted. This process repeats 8 times and the conversion of Frame N of 1.544M bit/s data rate to 2.048M bit/s data rate is completed. However, the F-bit of Frame N of the 1.544M bit/ s data rate is inserted as the 8th bit of the N of the 2.048M bit/s data rate (refer to Figure - 22). In the Receive Clock Slave Mode, the Receive Side System Common Clock (RSCCK) is provided by the system side. It is used as a common timing clock for all eight framers. The speed of the RSCCK can be 1.544MHz or 2.048MHz. When it is 2.048MHz, the RSCCK can be selected by the CMS (b4, T1/J1-078H) to be the same as the received data (2.048Mb/s), or double the received data (4.096 Mb/s). The CMS (b4, T1/J1-078H) of the eight framers should be set to the same value. If the speed of the RSCCK is double the received data stream, there will be two active edges in one bit duration. In this case, the RSD_RSCFS_EDGE (b5, T1/J1-078H) determines the active edge to update the signal on the RSDn, RSSIGn and RSFSn pins; however, the pulse on the RSCFS is always sampled on its first active edge.
Table - 20. T1/J1 Mode Receive System Interface in Different Operation Modes Operation Mode NonClock Slave Multiplexed Mode Mode Clock Master Mode Multiplexed Mode Data Pin RSDn RSDn RSDn RSDn MRSD Clock Pin RSCCK RSCCK RSCKn RSCKn MRSCCK Framing Pin RSCFS/RSFSn RSCFS/RSFSn RSFSn RSFSn MRSCFS/MRSFS Signaling Pin Reference Clock No RSCKn RSSIGn No No No No No MRSSIG No
RSCK Reference External Signaling Full T1/J1 Fractional T1/J1
Table - 21. Operation Mode Selection in T1/J1 Receive Path
RSCCK2M / RSCCK8M (b4, T1/J1-001H) / (b3, T1/J1-001H) 00 / 10 * 00 01 (in any of the eight framers) IMODE[1:0] (b7~6, T1/J1-001H) 10 11 01 00 11 Operation Mode Receive Clock Slave RSCK Reference Receive Clock Slave External Signaling Receive Clock Master Full T1/J1 Receive Clock Master Fractional T1/J1 Receive Multiplexed
Note: * When the RSCCK2M / RSCCK8M are `00', the system clock rate is 1.544MHz. When the RSCCK2M / RSCCK8M are `10', the system clock rate is 2.048MHz, i.e., T1/J1 mode E1 rate.
47
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
1.544M bit/s
F
CH1
CH2
CH3
CH4
CH5
CH24
F
CH1
2.048M bit/s
TS0
TS1
TS2
TS3
TS4
TS5
TS6
TS31
TS0
TS1
inserted
the 8th bit
inserted
inserted the 8th bit
Figure - 22. T1/J1 To E1 Format Conversion In the Receive Clock Slave Mode, the Receive Side System Common Frame Pulse (RSCFS) is used as a common framing signal to align the data stream for all eight framers. The RSCFS asserts on each F-bit and its valid polarity is configured by the FPINV (b6, T1/J1-078H). In the Receive Clock Slave Mode, the RSFSn can indicate each Fbit of SF/ESF, every second F-bit or the first F-bit of every 12 frames (in SF format) / every 24 frames (in ESF format). All the indications are selected by the RSFSP (b2, T1/J1-001H) and ALTIFP (b1, T1/J1-001H). The valid polarity of the RSFSn is configured by the FPINV (b6, T1/J1078H). The Receive Clock Slave Mode includes two sub-modes: Receive Clock Slave RSCK Reference Mode and Receive Clock Slave External Signaling Mode. Note that if the receive system interface is configured to operate in T1/J1 mode E1 rate, framer 1, 3, 5, 7 must be configured in the same sub-mode and framer 2, 4, 6, 8 must be configured in the same sub-mode. 3.11.2.1.1 Receive Clock Slave RSCK Reference Mode In this mode (refer to Figure - 7), the data on the system interface is clocked by the RSCCK. The active edge of the RSCCK to sample the data on the RSCFS pin or to update the data on the RSDn and RSFSn pins is determined by the following bits in the registers (refer to Table 22). Table - 22. Active Edge Selection of RSCCK (in T1/J1 Receive Clock Slave RSCK Reference Mode)
the Bit Determining the Active Edge of the RSCCK RSCFSFALL (b1, T1/J1-003H) RSCCKRISE (b0, T1/J1-003H)
RSCFS RSFSn RSDn
Note: The RSCFSFALL (b1, T1/J1-003H) of the eight framers should be set to the same value to ensure the RSCFS for the eight framers is sampled on the same active edge. It is a special case when the CMS (b4, T1/J1-078H) is logic 1 and the RSCFSFALL (b1, T1/J1-003H) is not equal to RSCCKRISE (b0, T1/J1003H). The RSD_RSCFS_EDGE (b5, T1/J1-078H) is invalid and the signals on the RSDn and the RSFSn pins are updated on the first active edge of RSCCK.
Figure - 23 to 25 show the functional timing examples. Bit 1 of each channel is the first bit to be output.
The CMS (b4, T1/J1-078H) is logic 0 and the bankplane rate is 1.544Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 0 and the RSCCKRISE (b0, T1/J1-003H) is logic 0. The channel offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 CH24 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5
(The RSCKn is selected by the RSCKSEL (b5, T1/J1-001H) to output a jitter attenuated 1.544MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed LRCKn divided by 193).)
Figure - 23. T1/J1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 1
48
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b4, T1/J1-078H) is logic 0 and the bankplane clock rate is 2.048Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 0 and the RSCCKRISE (b0, T1/J1-003H) is logic 1. The channel offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 CH24 6 7 8 P X X X X X X F 1 2 3 4 CH1 5 6
DUMMY
(The 'X' represent the filled bits and has no meaning.)
(The RSCKn is selected by the RSCKSEL (b5, T1/J1-001H) to output a jitter attenuated 1.544MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed LRCKn divided by 193).)
Figure - 24. T1/J1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 2
The CMS (b4, T1/J1-078H) is logic 1, i.e., the bankplane clock rate is 4.096Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 0 and the RSCCKRISE (b0, T1/J1-003H) is logic 1. When the channel offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn 1 2 3 4 5 CH24 6 7 8 P X X X X X X F 1 2 3 4 CH1 5 6
RSDn
DUMMY
(The 'X' represents the filled bits and has no meaning.)
(The RSCKn is selected by the RSCKSEL (b5, T1/J1-001H) to output a jitter attenuated 1.544MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed LRCKn divided by 193).)
Figure - 25. T1/J1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 3
49
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Besides all the common functions described in the Receive Clock Slave mode, the special feature in this mode is that the multi-functional pin RSCKn/RSSIGn is used as RSCKn to output a reference clock. The RSCKn can be selected by the RSCKSEL (b5, T1/J1-001H) to output a jitter attenuated 1.544MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed LRCKn divided by 193). 3.11.2.1.2 Receive Clock Slave External Signaling Mode In this mode (refer to Figure - 10), the data on the system interface is clocked by the RSCCK. The active edge of the RSCCK to sample the pulse on the RSCFS or to update the data on the RSDn, RSFSn and RSSIGn pins is determined by the following bits in the registers (refer to Table - 23). Table - 23. Active Edge Selection of RSCCK (in T1/J1 Receive Clock Slave External Signaling Mode)
the Bit Determining the Active Edge of the RSCCK RSCFSFALL (b1, T1/J1-003H) RSCCKRISE (b0, T1/J1-003H)
Figure - 26 to 28 show the functional timing examples. Bit 1 of each channel is the first bit to be output. Besides all the common functions described in the Receive Clock Slave mode, the special feature in this mode is that the multi-functional pin RSCKn/RSSIGn is used as RSSIGn to output the extracted signaling bits. The extracted signaling bits are channel aligned with the data on the RSDn pin (refer to Figure - 6). 3.11.2.2 Receive Clock Master Mode In the Receive Clock Master mode, each framer uses its own clock signal on RSCKn pin and framing signal on RSFSn pin to output the data on each RSDn pin. In the Receive Clock Master Mode, the bit rate on the RSDn pin is 1.544Mb/s. In the Receive Clock Master Mode, the RSFSn can indicate each Fbit of SF/ESF, every second F-bit or the first F-bit of every 12 frames (in SF format) / every 24 frames (in ESF format). All the indications are selected by the RSFSP (b2, T1/J1-001H) and ALTIFP (b1, T1/J1-001H). The valid polarity of the RSFSn is configured by the FPINV (b6, T1/J1078H). In the Receive Clock Master Mode, the data on the system interface is clocked by the RSCKn. The active edge of the RSCKn to update the data on the RSDn and RSFSn is determined by the RSCKRISE(b3, T1/ J1-003H). The Receive Clock Master Mode includes two sub-modes: Receive Clock Master Full T1/J1 Mode and Receive Clock Master Fractional T1/ J1 Mode.
RSCFS RSFSn RSDn RSSIGn
Note: The RSCFSFALL (b1, T1/J1-003H) of the eight framers should be set to the same value to ensure the RSCFS for the eight framers is sampled on the same active edge. It is a special case when the CMS (b4, T1/J1-078H) is logic 1 and the RSCFSFALL (b1, T1/J1-003H) is not equal to RSCCKRISE (b0, T1/J1003H). The RSD_RSCFS_EDGE (b5, T1/J1-078H) is invalid and the signal on the RSDn, RSSIGn and the RSFSn pins are updated on the first active edge of RSCCK.
The CMS (b4, T1/J1-078H) is logic 0 and the bankplane clock rate is 1.544Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 1 and the RSCCKRISE (b0, T1/J1-003H) is logic 0. The channel offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn RSDn 1 2 3 4 5 CH24 RSSIGn X X X X A B C D X X X X 6 7 8 F 1 2 3 4 CH1 X X X X X X X 5 6 7 8 1 2 3 CH2 X X A 4 5
(The 'X' represent the filled bits and has no meaning.)
Figure - 26. T1/J1 Receive Clock Slave External Signaling Mode - Functional Timing Example 1
50
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b4, T1/J1-078H) is logic 0 and the bankplane clock rate is 2.048Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 1 and the RSCCKRISE (b0, T1/J1-003H) is logic 1. The channel offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn 1 2 3 4 5 CH24 RSSIGn X X X X A B C D P X X X 6 7 8 P X X X X X X F 1 2 3 4 CH1 X X X X X X A B 5 6
RSDn
DUMMY X X
(The 'X' represents the filled bits and has no meaning.)
Figure - 27. T1/J1 Receive Clock Slave External Signaling Mode - Functional Timing Example 2
The CMS (b4, T1/J1-078H) is logic 1, i.e., the bankplane clock rate is 4.096Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 1 and the RSCCKRISE (b0, T1/J1-003H) is logic 1. RSCFS RSCCK When the RSD_RSCFS_EDGE (b5, T1/J1-078H) is logic 1: RSFSn RSDn 1 2 3 4 5 CH24 RSSIGn X X X X A B C D P X X X 6 7 8 P X X X X X X F 1 2 3 4 CH1 X X X X X X A B 5 6
DUMMY X X
When the RSD_RSCFS_EDGE (b5, T1/J1-078H) is logic 0: RSFSn 1 2 3 4 5 CH24 RSSIGn X X X X A B C D P X X 6 7 8 P X X X X X X F 1 2 3 4 CH2 X X X X X X X A B 5 6
RSDn
DUMMY X X
(The 'X' represents the filled bits and has no meaning.)
Figure - 28. T1/J1 Receive Clock Slave External Signaling Mode - Functional Timing Example 3
51
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.11.2.2.1 Receive Clock Master Full T1/J1 Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode (refer to Figure - 13) is that the RSCKn is a standard 1.544MHz clock, and the data in all the 24 channels in a standard T1/J1 frame is clocked out by the RSCKn. Figure - 29 shows the functional timing examples. Bit 1 of each channel is the first bit to be output. 3.11.2.2.2 Receive Clock Master Fractional T1/J1 Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode (refer to Figure - 15) is that the RSCKn is a gapped 1.544MHz clock (no clock signal during the selected channel). The RSCKn is gapped during those channels with their EXTRACT (b2, T1/J1-RPLC-indirect registers - 01~18H) in Receive Payload Control are logic 0 and clocks out during those channels with their EXTRACT (b2, T1/J1-RPLC-indirect registers - 01~18H) are logic 1. The data in the corresponding gapped channel is a don't care condition. Figure - 30 shows the functional timing examples. Bit 1 of each channel is the first bit to be output. 3.11.2.3 Receive Multiplexed Mode In this mode (refer to Figure - 17), two multiplexed buses are used to receive the data from all eight framers. The data from up to four framers is byte-interleaved output on one of the two multiplexed buses. The multiplexed bus is selected by the MRBS (b7, T1/J1-003H). When the data from four framers are output on one multiplexed bus, the sequence of data is arranged by setting the channel offset TSOFF[6:0] (b6~0, T1/ J1-077H). The data from different framers on one multiplexed bus must be shifted at a different channel offset to avoid data mixing. Then the re-
ceived data of each framer can be controlled by the MRBC (b6, T1/J1003H) to output to the selected multiplexed bus or not. In the Receive Multiplexed mode, the data on the system interface are clocked by the MRSCCK. The active edge of the MRSCCK to sample the pulse on the MRSCFS and to update the data on the MRSD, MRSFS and MRSSIG are determined by the following bits in the registers (refer to Table - 24). Table - 24. Active Edge Selection of MRSCCK (in T1/J1 Receive Multiplexed Mode)
the Bit Determining the Active Edge of the MRSCCK RSCFSFALL (b1, T1/J1-003H) RSCCKRISE (b0, T1/J1-003H)
MRSCFS MRSFS MRSD MRSSIG
Note: When the RSCFSFALL/RSCCKRISE of any of the eight framers is configured as logic 1, all the others are taken as logic 1. That is, the RSCFSFALL/RSCCKRISE should be configured to the same value in Receive Multiplexed mode. It is a special case when the CMS (b4, T1/J1-078H) is logic 1 and the RSCFSFALL (b1, T1/J1-003H) is not equal to RSCCKRISE (b0, T1/J1003H). The RSD_RSCFS_EDGE (b5, T1/J1-078H) is invalid and the signal on the MRSD, MRSSIG and the MRSFS pins are updated on the first active edge of RSCCK.
RSCK is 1.544M RSCKn When the RSCKRISE (b3, T1/J1-003H) is logic 0: RSFSn RSDn 1 2 3 4 5 CH24 When the RSCKRISE (b3, T1/J1-003H) is logic 1: RSFSn RSDn 1 2 3 4 5 CH24 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5
Figure - 29. T1/J1 Receive Clock Master Full T1/J1 Mode - Functional Timing Example
52
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
RSCK is 1.544M. In this example, RSCK is supposed to be held in inactive state during CH2. When the RSCKRISE (b3, T1/J1-003H) is logic 0: RSCKn RSFSn RSDn 4 5 CH24 When the RSCKRISE (b3, T1/J1-003H) is logic 1: RSCKn RSFSn RSDn 4 5 CH24 6 7 8 X 1 2 3 4 CH1 5 6 7 8 6 7 8 X 1 2 3 4 CH1 5 6 7 8
Don't Care
1
2
Don't Care
1
2
Figure - 30. T1/J1 Receive Clock Master Fractional T1/J1 Mode - Functional Timing Example In the Receive Multiplexed mode, the Multiplexed Receive Side System Common Clock (MRSCCK) is provided by the system side. It is used as a common timing clock for all eight framers. The frequency of the MRSCCK can be selected by the CMS (b4, T1/J1-078H) to be the same as the bit rate of the received data stream (8.192Mb/s), or double the bit rate of the received data stream (16.384 Mb/s). If the frequency of the RSCCK is double the bit rate of the received data stream, there will be two active edges in one bit duration. In this case, the RSD_RSCFS_EDGE (b5, T1/J1-078H) determines the active edge to update the signal on the MRSD, MRSSIG and MRSFS pin; however, the pulse on the MRSCFS is always sampled on its first active edge. If the CMS (b4, T1/J1-078H) or the RSD_RSCFS_EDGE (b5, T1/J1-078H) of any of the eight framers is configured as logic 1, all the others are taken as logic 1. That is, the CMS (b4, T1/J1-078H) and the RSD_RSCFS_EDGE (b5, T1/J1-078H) of the eight framers should be configured to the same value in the Receive Multiplexed mode. In the Receive Multiplexed mode, the Multiplexed Receive Side System Common Frame Pulse (MRSCFS) is used as a common framing signal to align the data streams on the two multiplexed buses. The MRSCFS is asserted on the F-bit. The valid polarity of the MRSCFS is configured by the FPINV (b6, T1/J1-078H). The FPINV (b6, T1/J1078H) of the eight framers should be set to the same value. In the Receive Multiplexed mode, the bit rate on the MRSD pin is 8.192Mb/s. In the Receive Multiplexed mode, regardless of the setting in the RSFSP (b2, T1/J1-001H) and ALTIFP (b1, T1/J1-001H), the MRSFS can only indicate each F-bit of SF/ESF of the selected first framer. The valid
53
polarity of the RSFSn is configured by the FPINV (b6, T1/J1-078H). The FPINV (b6, T1/J1-078H) of the eight framers should be set to the same value. In the Receive Multiplexed mode, the MRSSIG outputs extracted signaling. The extracted signaling bits are channel aligned with the data outputted on the MRSD. Figure - 31 & 32 show the functional timing examples. Bit 1 of each channel is the first bit to be output. 3.11.2.4 Parity Check In all the above modes except for the Receive Clock Slave Fractional T1/J1 mode, if the RPRTYE (b0, T1/J1-002H) is logic 1, parity check can be conducted over the bits in the previous frame and the result is inserted into the F-bit on the RSDn/MRSD and RSSIGn/MRSSIG pin. The even parity or odd parity is selected by the RPTYP (b1, T1/J1-002H) and whether the F-bit is calculated or not is determined by the PTY_EXTD (b3, T1/J1-002H).
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b4, T1/J1-078H) is logic 0, i.e., the bankplane clock rate is 8.192Mbit/s. The RSCCKRISE(b0, T1/J1-003H) is logic 1 and the RSCFSFALL (b1, T1/J1-003H) is logic 0. In this example, Framer1 to Frame4 are supposed to be multiplexed to one multiplexed bus. MRSCFS
MRSCCK When the TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF_EN of the four Framers are set to logic 0: MRSFS MRSD
7
8
P Parity bit
X
X
X
X
X
X
F
P
X
X
X
X
X
X
F
P
X
X
X
X
X
X
F
P
X
X
X
X
X
X
F F-bit
1
2
3
4
5
6
7
8
Framer1 X X X X X X
F-bit Parity bit X P X X
Framer2 X X X X
F-bit Parity bit X P X X
Framer3 X X X X
F-bit Parity bit X P X X
Framer4 X X X X
Framer1_CH1 X X X X A B C D
MRSSIG
C
D
P
X
(The 'X' represents the filled bits and has no meaning.)
Figure - 31. T1/J1 Receive Multiplexed Mode - Functional Timing Example 1
The CMS (b4, T1/J1-078H) is logic 1, i.e., the bankplane clock rate is 16.384Mbit/s. The RSCCKRISE(b0, T1/J1-003H) is logic 1 and the RSCFSFALL (b1, T1/J1-003H) is logic 1. In this example, Framer1 to Frame4 are supposed to be multiplexed to one multiplexed bus. The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF_EN of the four Framers are set to logic 0: MRSCFS
MRSCCK When the RSD_RSCFS_EDGE (b5, T1/J1-078H) is logic 0: MRSFS MRSD 7 8 P Parity bit MRSSIG C D P X X X X X X X X F P X X X X X X F P X X X X X X F P X X X X X X F F-bit X X X X X X 1 2 3 4 5 6 7 8
Framer1 X X X X
F-bit Parity bit X P X X
Framer2 X X X X
F-bit Parity bit X P X X
Framer3 X X X X
F-bit Parity bit X P X X
Framer4 X X
Framer1_CH1 X A B C D
When the RSD_RSCFS_EDGE (b5, T1/J1-078H) is logic 1: MRSFS MRSD 7 8 P Parity bit MRSSIG C D P X X X X X X X F P X X X X X F P X X X X X F P X X X X X 3 6 7
X
X
X
X
F F-bit
1
2
4
5
8
Framer1 X X X X
F-bit Parity bit X P X X
Framer2 X X X X
F-bit Parity bit X P X X
Framer3 X X X X
F-bit Parity bit X P X X
Framer4 X X X X
Framer1_CH1 X X X X A B C D
X
(The 'X' represents the filled bits and has no meaning.)
Figure - 32. T1/J1 Receive Multiplexed Mode - Functional Timing Example 2
54
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.11.2.5 Offset When the system clock rate is 2.048MHz (in Receive Clock Slave T1/ J1 mode E1 rate mode) or 8.192MHz (in Receive Multiplexed mode), channel offset and/or bit offset between the RSCFS and the start of the corresponding frame on the RSDn/MRSD (and RSSIGn/MRSSIG) can be configured. Bit offset is disabled when the CMS (b4, T1/J1-078H) is logic 1. The channel offset is configured in the TSOFF[6:0] (b6~0, T1/J1077H). The TSOFF[6:0] (b6~0, E1-013H) give a binary representation. Enabled by the BOFF_EN (b3, T1/J1-078H), the bit offset is configured in the BOFF[2:0] (b2~0, T1/J1-078H). The bit offset follows the Concentration Highway Interface (CHI) specification (refer to Table 25). The CET (clock edge transmit) is counted from the active edge of the RSCFS/MRSCFS (refer to the example in Figure - 33). The pulse on the RSFSn/MRSFS and the signal on the RSSIGn/MRSSIG (if exists) are aligned to the RSDn/MRSD. Table - 25. Receive System Interface Bit Offset RSCFSFALL RSCCKRISE (b1, T1/J1-003) (b0, T1/J1-003H) 1 0 1 1 0 0 0 1
3.11.2.6 Output On RSDn/MRSD & RSSIGn/MRSSIG In all the five modes, the RSDn/MRSD and the RSSIGn/MRSSIG pin can be configured by the TRI[1:0] (b5~4, T1/J1-003H) of the corresponding framer to be in high impedance state or to output the processed data stream.
000 2 1 1 2
001 4 3 3 4
010 6 5 5 6
BOFF[2:0] (b2~0, T1/J1-078H) 011 100 101 8 10 12 7 9 11 7 9 11 8 10 12
110 14 13 13 14
111 16 15 15 16
CET
For example: when RSCFSFALL (b1, T1/J1-003H) = 1, RSCCKRISE (b0, T1/J1-003H) = 0 starting edge (CET=0) 1 2 3 4 5 CET=6 RSCFS RSCCK The bit offset is 0: RSDn 1 2 3 4 5 6 7 8 P X X X X X X F 1 2 3 CH1 4
CH24
DUMMY
The bit offset is set as: BOFF_EN (b3, T1/J1-078H) = 1, BOFF[2:0] (b2~0, T1/J1-078H) = 010; i.e. the CET = 6: RSDn 1 2 3 4 5 6 7 8 P X X X X X X F 1 2 3 CH1 4
CH24
DUMMY
Figure - 33. Receive Bit Offset in T1/J1 Mode
55
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.12 PRBS GENERATOR / DETECTOR (PRGD)
The PRBS Generator/Detector is shared by eight framers. It can be assigned to any of the 8 framers at one time. The PRGD, together with the Receive / Transmit Payload Control blocks, is used to test the data stream. 3.12.1 E1 MODE The PRBS Generator/Detector is a global control block. Any one of the eight framers can be linked to the pattern generator or detector by the PRGDSEL[2:0] (b7~5, E1-00CH). The pattern can be inserted in either the transmit or receive direction, and detected in the opposite direction. The direction is determined by the RXPATGEN (b2, E1-00CH). The pattern can be generated or detected in unframed or framed mode. The selection is made by the UNF_GEN (b1, E1-00CH) or UNF_DET (b0, E1-00CH) respectively. In unframed mode, all the 32 timeslots are replaced or extracted and the specification of the TEST (b7, E1-RPLC-indirect registers - 20~3FH or b3, E1-TPLC-indirect registers - 20~3FH) in Receive / Transmit Payload Control blocks are ignored. In framed mode, the timeslot is specified by the TEST (b7, E1-RPLC-indirect registers 20~3FH or b3, E1-TPLC-indirect registers - 20~3FH). Pattern Generator The repetitive or pseudo-random pattern selected by the PS (b4, E1070H) is located in the PI[31:0] (b7~0, E1-078H & b7~0, E1-079H & b7~0, E1-07AH & b7~0, E1-07BH). However, the length of the valid data in the PI[31:0] is determined by the PL[4:0] (b4~0, E1-072H). If the repetitive pattern is selected, the valid PI[X:0] (X is equal to one number of the 31 to 1) reflect its content directly. If the pseudo-random pattern is selected, the valid PI[X:0] are its initial value and the feedback tap position (refer to Figure - 34) is determined by the PT[4:0] (b4~0, E1-073H). A single bit error can be inserted by setting the EVENT (b3, E1-074H) to 1, or continuous bit errors can be inserted at a bit error rate determined by the EIR[2:0] (b2~0, E1-074H). Before replacing the data in the assigned direction, the pattern can be inverted with the TINV (b3, E1070H) enabled.
Pattern Detector The extracted data from the assigned direction are compared with a repetitive or pseudo-random pattern selected by the PS (b4, E1-070H). Before being compared, the data can be inverted with the RINV (b2, E1070H) enabled. The extracted data are then compared with a 48-bit fixed window loaded with the pattern. This process goes on until the data coincide with the pattern. When they are synchronized, it is indicated by the SYNCV (b4, E1-071H). Bit errors in the synchronized data are indicated in the BEI (b2, E1-071H). When there are more than 10-bit errors in the fixed 48-bit window, the extracted data are out of synchronization. Automatic search for the re-synch will be done with the AUTOSYNC (b1, E1-070H) configured, or manual search can be done when there is a transition from low to high on the MANSYNC (b0, E1-070H). A manual search is recommended to execute to ensure the PRGD operates correctly when there is any setting change of the PRGD registers or the detector data source changes. Selected by the PDR[1:0] (b7~6, E1-070H), the PD[31:0] (b7~0, E107CH & b7~0, E1-07DH & b7~0, E1-07EH & b7~0, E1-07FH) can contain the received pattern, the total error count or the total number of received bits. They update when the defined intervals are initiated. The intervals equal 1 second when the AUTOUPDATE (b0, E1-000H) is set in the corresponding framer. They can also be updated by writing to any of the PD[31:0] (b7~0, E1-07CH & b7~0, E1-07DH & b7~0, E1-07EH & b7~0, E1-07FH), or to the E1 Chip ID / Global PMON Update register (E1-009H). The update will be indicated by the XFERI (b1, E1-071H). If they are not read in the defined intervals, the PD[31:0] (b7~0, E1-07CH & b7~0, E1-07DH & b7~0, E1-07EH & b7~0, E1-07FH) will be overwritten with new data. The overwritten condition is indicated by the OVR (b0, E1-071H). 3 kinds of interrupts can be generated by this block: - bit errors; - synchronization status change (indicated in the SYNCI [b3, E1071H]); - the PD[31:0] (b7~0, E1-07CH & b7~0, E1-07DH & b7~0, E1-07EH & b7~0, E1-07FH) are updated. When the interrupts are enabled by the BEE (b6, E1-071H), SYNCE
TAP[0] SET
TAP[1] SET
TAP[2] SET
TAP[31]
D
Q
D
Q
D
Q
D
SET
Q
CLR Q
CLR Q
CLR Q
CLR Q
Figure - 34. PRBS Pattern Generator
56
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
(b7, E1-071H) and XFERE (b5, E1-071H) respectively, the INT pin is asserted. 3.12.2 T1 / J1 MODE The PRBS Generator/Detector is a global control block. Any one of the eight framers can be linked to pattern generator or detector by the PRGDSEL[2:0] (b7~5, T1/J1-00FH). The pattern can be inserted in either the transmit or receive direction, and detected in the opposite direction. The direction is determined by the RXPATGEN (b2, T1/J1-00FH). The pattern can be generated or detected in unframed or framed mode. The selection is made by the UNF_GEN (b1, T1/J1-00FH) or UNF_DET (b0, T1/J1-00FH) respectively. In unframed mode, all the 24 channels are replaced or extracted and the specification of the TEST (b3, T1/J1RPLC-indirect registers - 01~18H or b3, T1/J1-TPLC-indirect registers 01~18H) in Receive / Transmit Payload Control blocks are ignored. In framed mode, the channel is specified by the TEST (b3, T1/J1-RPLC-indirect registers - 01~18H or b3, T1/J1-TPLC-indirect registers - 01~18H). However, fractional T1/J1 signal can be replaced or extracted in the specified channel when the Nx56k_GEN (b4, T1/J1-00FH) or Nx56k_DET (b3, T1/J1-00FH) is set respectively. Pattern Generator The repetitive or pseudo-random pattern selected by the PS (b4, T1/ J1-060H) is located in the PI[31:0] (b7~0, T1/J1-068H & b7~0, T1/J1069H & b7~0, T1/J1-06AH & b7~0, T1/J1-06BH). However, the length of the valid data in the PI[31:0] is determined by the PL[4:0] (b4~0, T1/J1062H). If the repetitive pattern is selected, the valid PI[X:0] (X is valid for 1 to 31) reflect its content directly. If the pseudo-random pattern is selected, the valid PI[X:0] are its initial value and the feedback tap position (refer to Figure - 34) is determined by the PT[4:0] (b4~0, T1/J1-063H). A single bit error can be inserted by setting the EVENT (b3, T1/J1-064H), or continuous bit errors can be inserted at a bit error rate determined by the EIR[2:0] (b2~0, T1/J1-064H). Before replacing the data in the assigned direction, the pattern can be inverted with the TINV (b3, T1/J1060H) enabled. Pattern Detector The extracted data from the assigned direction are compared with a repetitive or pseudo-random pattern selected by the PS (b4, T1/J1060H). Before being compared, the data can be inverted with the RINV (b2, T1/J1-060H) enabled. The extracted data are then compared with a 48-bit fixed window loaded with the pattern. This process continues until the data coincide with the pattern. They are then synchronized with an indication in the SYNCV (b4, T1/J1-061H). Bit errors in the synchronized data are indicated in the BEI (b2, T1/J1-061H). When there are more than 10-bit errors in the fixed 48-bit window, the extracted data are out of synchronization. Automatic search for the re-synch will be done with the AUTOSYNC (b1, T1/J1-060H) configured, or manual search can be done when there is a transition from low to high on the MANSYNC (b0, T1/J1-060H). A manual search is recommended to execute to ensure the PRGD operates correctly when there is any setting change of the PRGD registers or the detector data source changes. Selected by the PDR[1:0] (b7~6, T1/J1-060H), the PD[31:0] (b7~0, T1/J1-06CH & b7~0, T1/J1-06DH & b7~0, T1/J1-06EH & b7~0, T1/J106FH) can contain the received pattern, the total error count or the total number of received bits. They update when the defined intervals are initiated. The intervals equal 1 second when the AUTOUPDATE (b0, T1/
J1-000H) is set in the corresponding framer. They can also be updated by writing to any of the PD[31:0] (b7~0, T1/J1-06CH & b7~0, T1/J106DH & b7~0, T1/J1-06EH & b7~0, T1/J1-06FH), or to the T1/J1 Chip ID / Global PMON Update register (T1/J1-00CH). The update will be indicated by the XFERI (b1, T1/J1-061H). If they are not read in the defined intervals, the PD[31:0] (b7~0, T1/J1-06CH & b7~0, T1/J1-06DH & b7~0, T1/J1-06EH & b7~0, T1/J1-06FH) will be overwritten with new data. The overwritten condition is indicated by the OVR (b0, T1/J1-061H). 3 kinds of interrupts can be generated by this block: - bit errors; - synchronization status change (indicated in the SYNCI [b3, T1/J1061H]); - the PD[31:0] (b7~0, T1/J1-06CH & b7~0, T1/J1-06DH & b7~0, T1/ J1-06EH & b7~0, T1/J1-06FH) are updated. When the interrupts are enabled by the BEE (b6, T1/J1-061H) SYNCE (b7, T1/J1-061H) and XFERE (b5, T1/J1-061H) respectively, the INT pin is asserted.
3.13 TRANSMIT SYSTEM INTERFACE (TRSI)
The Transmit System Interface determines how to input the data to the chip. The input data to the eight framers can be aligned with each other or inputted independently. The timing clocks and framing pulses can be provided by the system back-plane common to eight framers or provided for eight framers individually. The Transmit System Interface supports various configurations to meet various requirements in different applications. 3.13.1 E1 MODE In E1 mode, the Transmit System Interface can be set in Nonmultiplexed Mode or Multiplexed Mode. In Non-multiplexed Mode, the TSDn pin is used to input the data to each framer at the bit rate of 2.048 Mb/s. While in the Multiplexed Mode, the data input to the eight framers are byte interleaved from two high speed data streams and input on the MTSD1 and MTSD2 pins at the bit rate of 8.192 Mb/s. In the Non-multiplexed Mode, if the timing signal for clocking data on TSDn pin is provided by the system side and shared by all eight framers, the Transmit System Interface should be set in Transmit Clock Slave mode. If the timing signal for clocking data on each TSDn pin is provided from each line side (processed timing signal), the Transmit System Interface should be set in Transmit Clock Master mode. In the Non-multiplexed Mode, if there is a common framing pulse provided by the system side for the eight framers, the Transmit System Interface should be set in Transmit Clock Slave mode. If there is no common framing pulse, the Transmit System Interface should be set in Transmit Clock Master mode. In the Transmit Clock Slave mode, if the multi-function pin TSFSn/ TSSIGn is used to output the framing indication pulse, the Transmit System Interface is in Transmit Clock Slave TSFS Enable mode. If the TSFSn/TSSIGn is used to input the signaling bits to be inserted, the Transmit System Interface is in Transmit Clock Slave External Signaling mode. In the Transmit Clock Master mode, the multi-function pin TSFSn/ TSSIGn is used as TSFSn to input the framing indication pulse. Table - 26 summarizes the transmit system interface in different operation modes. To set the transmit system interface of each framer into various operation modes, the registers must be configured as Table - 27.
57
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 26. E1 Mode Transmit System Interface in Different Operation Modes Operation Mode NonClock Slave TSFS Enable Multiplexed Mode External Signaling Mode Clock Master Mode Multiplexed Mode Data Pin TSDn TSDn TSDn MTSD Clock Pin TSCCKB TSCCKB LTCKn MTSCCKB Framing Pin TSCFS & TSFSn TSCFS TSFSn MTSCFS Signaling Pin No TSSIGn No MTSSIG Reference Clock TSCCKA TSCCKA TSCCKA & TSCCKB TSCCKA
Table - 27. Operation Mode Selection in E1 Transmit Path
RATE[1:0] (b1~0, E1-018H) 01 11(All the eight framers should be set) TSCKSLV (b5, E1-018H) 1 0 1 TSSIG_EN (b6, E1-003H) 0 1 1 Operation Mode Transmit Clock Slave TSFS Enable Transmit Clock Slave External Signaling Transmit Clock Master Transmit Multiplexed
3.13.1.1 Transmit Clock Slave Mode In the Transmit Clock Slave mode, the Transmit Side System Common Clock B (TSCCKB) is provided by the system side. It is used as a common timing clock for all eight framers. The speed of the TSCCKB can be selected by the CMS (b2, E1-018H) to be the same as the data to be transmitted (2.048MHz), or twice the data (4.096MHz). The CMS (b2, E1-018H) of the eight framers should be set to the same value. If the speed of the TSCCKB is twice the data to be transmitted, there will be two active edges in one bit time. In this case, the COFF (b4, E1-01CH) determines the active edge to sample the signal on the TSDn and TSSIGn pins and the active edge to update the pulse on the TSFSn pin; however, the pulse on the TSCFS is always sampled on its first active edge. In the Transmit Clock Slave mode, the Transmit Side System Common Clock A (TSCCKA) is provided by the system side. It is used as one of the reference clocks for the transmit jitter attenuator DPLL for all eight framers (refer to the Transmit Clock for details). In the Transmit Clock Slave mode, the Transmit Side System Common Frame Pulse (TSCFS) is used as a common framing signal to align the data streams for the eight framers. The TSCFS is asserted on each
Basic Frame or Multi-Frame indicated by the FPTYP (b1, E1-019H). The valid polarity is congifured by the FPINV (b3, E1-019H). In the Transmit Clock Slave mode, the bit rate on the TSDn pin is 2.048Mb/s. The Transmit Clock Slave Mode includes two sub-modes: Transmit Clock Slave TSFS Enable Mode and Transmit Clock Slave External Signaling Mode. 3.13.1.1.1 Transmit Clock Slave TSFS Enable Mode In this mode (refer to Figure - 35), the data on the system interface are clocked by the TSCCKB. The active edge of the TSCCKB used to sample the pulse on the TSCFS and the data on the TSDn and TSFSn are determined by the following bits in the registers (refer to Table - 28). Figure - 36 & 37 show the functional timing examples. Bit 1 of each timeslot is the first bit to be transmitted. Besides all the common functions described in the Transmit Clock Slave mode, the special feature in this mode is that the multi-functional pin TSFSn/TSSIGn is used as TSFSn to output a framing pulse to indicate the first bit of each Basic Frame.
TSCCKA TSCCKB TSCFS * TSD[1:8] * TSFS[1:8] * Transmit System Interface DPLL FIFO
LRCK[1:8]
LTCK[1:8] LTD[1:8]
Frame Generator
TRANSMITTER Note: * TSCFS, TSD, TSFS are timed to TSCCKB
Figure - 35. Transmit Clock Slave TSFS Enable Mode
58
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b2, E1-018H) is logic 0, i.e., the backplane clock rate is 2.048Mbit/s. The DE (b4, E1-018H) is logic 0 and the FE(b3, E1-018H) is logic 0. TSCCKB TSCFS TSDn 1 2 3 4 5 TS31 (When the TSFSRISE (b2, E1-002) is logic 0:) TSFSn (When the TSFSRISE (b2, E1-002) is logic 1:) TSFSn 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6
Figure - 36. E1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 1
The CMS (b2, E1-018H) is logic 1, i.e., the backplane clock rate is 4.096Mbit/s. The FE(b3, E1-018H) is logic 0 and the DE (b4, E1-018H) is logic 1. The COFF (b4, E1-01CH) is in its default value. TSCCKB TSCFS
TSDn
1
2
3
4
5 TS31
6
7
8
1
2
3
4
5 TS0
6
7
8
1
2
3
4 TS1
5
6
(When the TSFSRISE (b2, E1-002) is logic 0:) TSFSn (When the TSFSRISE (b2, E1-002) is logic 1:) TSFSn
Figure - 37. E1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 2
59
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 28. Active Edge Selection of TSCCKB (in E1 Transmit Clock Slave TSFS Enable Mode)
the Bit Determining the Active Edge of the TSCCKB FE (b3, E1-018H) DE (b4, E1-018H) TSFSRISE (b2, E1-002H)
Table - 29. Active Edge Selection of TSCCKB (in E1 Transmit Clock Slave External Signaling Mode)
the Bit Determining the Active Edge of the TSCCKB FE (b3, E1-018H) DE (b4, E1-018H)
TSCFS TSDn TSFSn
TSCFS TSDn TSSIGn
Note: If the FE is not equal to the DE, the active edge decided by the FE is one clock edge before the active edge decided by the DE. The FE (b3, E1-018H) of the eight framers should be set to the same value to ensure the TSCFS for the eight framers is sampled on the same active edge.
Note: If the FE is not equal to the DE, the active edge decided by the FE is one clock edge before the active edge decided by the DE. The FE (b3, E1-018H) of the eight framers should be set to the same value to ensure the TSCFS for the eight framers is sampled on the same active edge.
3.13.1.1.2 Transmit Clock Slave External Signaling Mode In this mode (refer to Figure - 38), the data on the system interface are clocked by the TSCCKB. The active edge of the TSCCKB used to sample the pulse on the TSCFS and the data on the TSDn and TSSIGn is determined by the following bits in the registers (refer to Table - 29). Figure - 39 & 40 show the functional timing examples. Bit 1 of each timeslot is the first bit to be transmitted.
Besides all the common functions described in the Transmit Clock Slave mode, the special feature in this mode is that the multi-functional pin TSFSn/TSSIGn is used as TSSIGn to input the signaling. The signaling on the TSSIGn pin may replace the data on TS16 when the CCS is disabled and the SIGSRC (b4, E1-TPLC-indirect registers 61~7FH) in the TPLC block is logic 0.
TSCCKA TSCCKB TSCFS * TSD[1:8] * TSSIG[1:8] * Transmit System Interface DPLL FIFO
LRCK[1:8]
LTCK[1:8] LTD[1:8]
Frame Generator TRANSMITTER
Note: * TSCFS, TSD, TSSIG are timed to TSCCKB
Figure - 38. Transmit Clock Slave External Signaling Mode
The CMS (b2, E1-018H) is logic 0, i.e., the bankplane clock rate is 2.048Mbit/s. The DE (b4, E1-018H) is logic 0 and the FE(b3, E1-018H) is logic 1. TSCCKB TSCFS TSDn 1 2 3 4 5 TS31 TSSIGn X X X X A B C D P X X X 6 7 8 1 2 3 4 5 TS0 X X X X X X X 6 7 8 1 2 3 4 TS1 X A B 5 6
(The 'X' represent the filled bits and has no meaning.)
Figure - 39. E1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 1
60
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b2, E1-018H) is logic 1, i.e., the bankplane clock rate is 4.096Mbit/s. The FE(b3, E1-018H) is logic 1 and the DE (b4, E1-018H) is logic 1. The COFF (b4, E1-01CH) is in its default value. TSCCKB
TSCFS TSDn
1
2
3
4
5 TS31
6
7
8
1
2
3
4
5 TS0
6
7
8
1
2
3
4 TS1
5
6
TSSIGn
X
X
X
X
A
B
C
D
P
X
X
X
X
X
X
X
X
X
X
X
A
B
(The 'X' represent the filled bits and has no meaning.)
Figure - 40. E1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2 3.13.1.2 Transmit Clock Master Mode In the Transmit Clock Master mode (refer to Figure - 41), the Transmit Side System Common Clock A (TSCCKA) and Transmit Side System Common Clock B (TSCCKB) provided by the system side are used as one of the reference clocks for the transmit jitter attenuator DPLL for all eight framers (refer to the Transmit Clock for details). In the Transmit Clock Master mode, the multi-functional pin TSFSn/ TSSIGn is used as TSFSn to output a framing pulse to indicate the first bit of each Basic Frame. In the Transmit Clock Master mode, the bit rate on the TSDn pin is 2.048Mb/s. In the Transmit Clock Master mode, each framer uses its own processed clock signal on LTCKn pin to sample/update the data on the system interface. The active edge of the LTCKn to sample the data on the TSDn pin is determinded by the DE (b4, E1-018H). The active edge of the LTCKn to update the pulse on the TSFSn pin is determinded by the TSFSRISE (b2, E1-002H). Figure - 42 shows the functional timing examples. Bit 1 of each
timeslot is the first bit to be transmitted. 3.13.1.3 Transmit Multiplexed Mode In this mode (refer to Figure - 43), two multiplexed buses are used to input the data to all eight framers. Selected by the MTBS (b4, E1-003H) in each framer, the data on one of the two multiplexed buses is byte-interleaved input to up to four framers. When each group of four framers are selected, the input sequence of the data on the multiplexed bus is arranged by setting the timeslot offset TSOFF[6:0] (b6~0, E1-01BH). The data to different framers from one multiplexed bus must be shifted to a different timeslot offset to avoid data mixing. Then the data on the multiplexed bus will be input to each of the four selected framers with a byte-interleaved manner. In the Transmit Multiplexed mode, the data on the system interface are clocked by the MTSCCKB. The active edge of the MTSCCKB to sample the data on the MTSCFS, MTSD and MTSSIG is determined by the following bits in the registers (refer to Table - 30).
TSCCKA TSCCKB
LRCK[1:8]
TSD[1:8] * TSFS[1:8] *
Transmit System Interface
Frame Generator
DPLL
LTCK[1:8] LTD[1:8]
TRANSMITTER Note: * TSD, TSFS are timed to LTCK
Figure - 41. Transmit Clock Master Mode
61
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
LTCK is 2.048M LTCKn When the TSFSRISE (b2, E1-002H) is logic 0 and the DE (b4, E1-018H) is logic 1: TSFSn TSDn 1 2 3 4 5 TS31 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6
When the TSFSRISE (b2, E1-002H) is logic 1 and the DE (b4, E1-018H) is logic 1: TSFSn TSDn
1
2
3
4
5 TS31
6
7
8
1
2
3
4
5 TS0
6
7
8
1
2
3
4 TS1
5
6
When the TSFSRISE (b2, E1-002H) is logic 1 and the DE (b4, E1-018H) is logic 0: TSFSn TSDn 1 2 3 4 5 TS31 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6
When the TSFSRISE (b2, E1-002H) is logic 0 and the DE (b4, E1-018H) is logic 0: TSFSn TSDn 1 2 3 4 5 TS31 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 4 TS1 5 6
Figure - 42. E1 Transmit Clock Master Mode - Functional Timing Example
62
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 30. Active Edge Selection of MTSCCKB (in E1 Transmit Multiplexed Mode)
the Bit Determining the Active Edge of the MTSCCKB FE (b3, E1-018H) DE (b4, E1-018H)
MTSCFS MTSD MTSSIG
Note: If the FE is not equal to the DE, the active edge decided by the FE is one clock edge before the active edge decided by the DE. The FE and the DE of the eight framers should be set to the same value respectively.
In the Transmit Multiplexed mode, the Multiplexed Transmit Side System Common Clock B (MTSCCKB) is provided by the system side. It is used as a common timing clock for all eight framers. The speed of the MTSCCKB can be selected by the CMS (b2, E1-018H) to be the same as the data to be transmitted (8.192MHz), or double the data (16.384MHz). If the speed of the MTSCCKB is double the data to be transmitted, there will be two active edges in one bit duration. In this case, the COFF (b4, E1-01CH) determines the active edge to sample the signal on the MTSD and MTSSIG pins and the active edge to update the pulse on the MTSFS pin; however, the pulse on the MTSCFS is always sampled on its first active edge. However, if the CMS (b2, E1-018H) or the COFF (b4, E1-01CH) of any of the eight framers is configured as logic 1, all the others are taken as logic 1. That is, the CMS (b2, E1018H) and the COFF (b4, E1-01CH) of the eight framers should be configured to the same value in the Transmit Multiplexed mode.
In the Transmit Multiplexed mode, the Transmit Side System Common Clock A (TSCCKA) is provided by the system side. It is used as one of the reference clocks for the transmit jitter attenuator DPLL for all eight framers (refer to the Transmit Clock for details). In the Transmit Multiplexed mode, the Multiplexed Transmit Side System Common Frame Pulse (MTSCFS) is used as a common framing signal to align data streams on the two multiplexed buses. The MTSCFS is asserted on each Basic Frame of the selected first framer. The valid polarity of the MTSCFS is congifured by the FPINV (b3, E1-019H). The FPINV (b3, E1-019H) of the eight framers should be set to the same value. In the Transmit Multiplexed mode, the bit rate on the MTSD pin is 8.192Mb/s. In the Transmit Multiplexed mode, the MTSSIG inputs the signaling bits to be inserted. The signaling bits are timeslot aligned with the data input from the MTSD. The signaling bits may replace the data on TS16 when the CCS is disabled and the SIGSRC (b4, E1-TPLC-indirect registers - 61~7FH) in the TPLC block is logic 0. Figure - 44 & 45 show the functional timing examples. Bit 1 of each timeslot is the first bit to be transmitted. 3.13.1.4 Parity Check In all the above four modes, parity check is calculated over the bits in the previous Basic Frame and the result is inserted into the first bit (MSB) of TS0 on the TSDn/MTSD pin. The even parity or odd parity is selected by the TPTYP (b7, E1-01AH) and whether the first bit of TS0 is calculated or not is determined by the PTY_EXTD (b3, E1-01AH). The parity error event will be captured by the TDI (b5, E1-01AH). The parity error will cause an interrupt on the INT pin if the TPTYE (b6, E1-01AH) is enabled.
TSCCKA The Other Four of the Framer #1~#8 Transmit System Interface FIFO DPLL Frame Frame Any Four of the Framer #1~#8 Generator Generator DPLLFIFO Frame DPLL DPLL FIFO Generator Frame DPLL Generator DPLL FIFO
MTSCCKB MTSCFS * MTSD[1:2] * MTSSIG[1:2] *
LRCK[1:8] LTCK[1:8] LTD[1:8]
Note: * MTSCFS, MTSD, MTSSIG are timed to MTSCCKB
Figure - 43. Transmit Multiplexed Mode
63
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b2, E1-018H) is logic 0, i.e., the bankplane clock rate is 8.192Mbit/s. The FE (b3, E1-018H) is logic 0 and the DE (b4, E1-018) is logic 0. In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus. The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the CHI and the BOFF[2:0] of the four Framers are set to logic 0: MTSCFS MTSCCKB MTSD 4 3 6 7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
5
6
7
8
1
2
4
5
8
1
Framer1_TS31 MTSSIG D X X X X A B C D X X X
Framer1_TS0 X A B C D X X X X
Framer2_TS0 A B C D X X X X
Framer3_TS0 A B C D X X X X
Framer4_TS0 A B C D
Line Interface (of any of the Framer1 to Framer4): LTCK n
LTDn
TS31-7
TS31-8
TS0-1
TS0-2
TS0-3
TS0-4
TS0-5
TS0-6
TS0-7
TS0-8
Figure - 44. E1 Transmit Multiplexed Mode - Functional Timing Example 1
The CMS (b2, E1-018H) is logic 1, i.e., the bankplane clock rate is 16.384Mbit/s. The FE (b3, E1-018H) is logic 1 and the DE (b4, E1-018) is logic 0. The COFF (b4, E1-01CH) is in its default value. In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus. The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the CHI and the BOFF[2:0] of the four Framers are set to logic 0: MTSCFS MTSCCKB
MTSD
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
Framer1_TS31 MTSSIG D X X X X A B C D X X X
Framer1_TS0 X A B C D X X X X
Framer2_TS0 A B C D X X X X
Framer3_TS0 A B C DX X X X
Framer4_TS0 A B C D
Line Interface (of any of the Framer1 to Framer4): LTCKn LTDn TS0-1 TS0-2 TS0-3 TS0-4 TS0-5 TS0-7 TS0-8
TS31-7
TS31-8
TS0-6
Figure - 45. E1 Transmit Multiplexed Mode - Functional Timing Example 2
64
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.13.1.5 Offset In the Transmit Clock Slave mode and Transmit Multiplexed mode, timeslot offset is enabled by setting a non-zero value into the TSOFF[6:0] (b6~0, E1-01BH). The timeslot offset is between the TSCFS/MTSCFS and the start of the corresponding frame to be transmitted on the TSDn/MTSD. The timeslot offset can be set in both single clock mode (CMS [b2, E1-018H] = 0) and double clock mode (CMS [b2, E1-018H] = 1). In all the above four modes, bit offset is enabled by setting a nonzero value into the BOFF[2:0] (b2~0, E1-01CH). In Transmit Clock Slave mode and Transmit Multiplexed mode, the bit offset is between the TSCFS/MTSCFS and the start of the corresponding frame to be transmitted on the TSDn/MTSD. The bit offset can be set in both single clock mode (CMS [b2, E1-018H] = 0) and double clock mode (CMS [b2, E1018H] = 1). However, if the CHI (b3, E1-01CH) is logic 0, the bit offset
value equals the setting in the BOFF[2:0] (b2~0, E1-01CH). That is, `000' in the BOFF[2:0] (b2~0, E1-01CH) means no bit offset; `001' in the BOFF[2:0] (b2~0, E1-01CH) means one bit offset, and so on (refer to the examples in Figure - 46 and Figure - 47). If the CHI (b3, E1-01CH) is logic 1, the bit offset configured in the BOFF[2:0] (b2~0, E1-01CH) meets the Concentration Highway Interface (CHI) specification (refer to Table - 31 and Table - 32). The CER (clock edge receive) is counted from the active edge of the TSCFS/MTSCFS (refer to the examples in Figure - 48 and Figure - 49). When the bit offset is configured, the signal on the TSSIGn/MTSSIG or the pulse on the TSFSn is aligned to the RSDn/MRSD. In Transmit Clock Master mode, the bit offset is between the TSFSn and the start of the corresponding frame to be transmitted on the TSDn. In this case, the CHI specification is not supported and the bit offset value equals the setting in the BOFF[2:0] (b2~0, E1-01CH) (refer to the example in Figure - 50).
Table - 31. Transmit System Interface Bit Offset (CHI [b3, E1-01CH] = 1, CMS [b2, E1-018H] = 0) FE DE (b3, E1-018H) (b4, E1-018H) 0 0 0 1 1 0 1 1 BOFF[2:0] (b2~0, E1-01CH) 011 100 10 12 9 11 9 11 10 12
000 4 3 3 4
001 6 5 5 6
010 8 7 7 8
101 14 13 13 14
110 16 15 15 16
111 18 17 17 18
CER
Table - 32. Transmit System Interface Bit Offset (CHI [b3, E1-01CH] = 1, CMS [b2, E1-018H] = 1) FE DE (b3, E1-018H) (b4, E1-018H) 0 0 0 1 1 0 1 1 BOFF[2:0] (b2~0, E1-01CH) 011 100 18 22 19 23 19 23 18 22
000 6 7 7 6
001 10 11 11 10
010 14 15 15 14
101 26 27 27 26
110 30 31 31 30
111 34 35 35 34
CER
For example: in Transmit Clock Slave mode, CMS (b2, E1-018H) = 0, DE (b4, E1-018H) = 0, FE (b3, E1-018H) = 0: TSCFS TSCCKB The CHI (b3, E1-01CH) = 0 and the bit offset is 0: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
The bit offset is set as: CHI (b3, E1-01CH) = 0, BOFF[2:0] (b2~0, E1-01CH) = 010; i.e. 2-bit offset: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
Figure - 46. Transmit Bit Offset in E1 Mode - 1
65
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
For example: in Transmit Clock Slave mode, CMS (b2, E1-018H) = 1, FE (b3, E1-018H) = 1, DE (b4, E1-018H) = 1: TSCFS TSCCKB The CHI (b3, E1-01CH) = 0 and the bit offset is 0: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
The bit offset is set as: CHI (b3, E1-01CH) = 0, BOFF[2:0] (b2~0, E1-01CH) = 010; i.e. 2-bit offset: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
Figure - 47. Transmit Bit Offset in E1 Mode - 2
For example: in Transmit Clock Slave mode, CMS (b2, E1-018H) = 0, DE (b4, E1-018H) = 0, FE (b3, E1-018H) = 0: starting edge (CER=0) 1 2 3 CER=4 TSCFS TSCCKB The CHI (b3, E1-01CH) = 0 and the bit offset is 0: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
The bit offset is set as: CHI (b3, E1-01CH) = 1, BOFF[2:0] (b2~0, E1-01CH) = 000; i.e. CER = 4: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
Figure - 48. Transmit Bit Offset in E1 Mode - 3
66
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
For example: in Transmit Clock Slave mode, CMS (b2, E1-018H) = 1, FE (b3, E1-018H) = 1, DE (b4, E1-018H) = 1: starting edge (CER=0) 12345CER=6 TSCFS TSCCKB The CHI (b3, E1-01CH) = 0 and the bit offset is 0: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
The bit offset is set as: CHI (b3, E1-01CH) = 1, BOFF[2:0] (b2~0, E1-01CH) = 000; i.e. CER = 6: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
Figure - 49. Transmit Bit Offset in E1 Mode - 4
For example: in Transmit Clock Master mode, DE (b4, E1-018H) = 1, TSFSRISE (b2, E1-002H) = 1: TSFSn LTCKn The bit offset is 0: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
The bit offset is set as: BOFF[2:0] (b2~0, E1-01CH) = 001; i.e. 1-bit offset: TSDn 1 2 3 4 TS31 5 6 7 8 1 2 3 4 5 TS0 6 7 8 1 2 3 TS2 4
Figure - 50. Transmit Bit Offset in E1 Mode - 5
67
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.13.2 T1 / J1 MODE In T1/J1 mode, the Transmit System Interface can be set in Nonmultiplexed Mode or Multiplexed Mode. In Non-multiplexed Mode, the TSDn pin is used to input the data to each framer at the bit rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed Mode, the data input to the eight framers are converted to 2.048 Mb/s format and byte interleaved from two high speed data streams and input on the MTSD1 and MTSD2 pins at the bit rate of 8.192 Mb/s. In the Non-multiplexed Mode, if the timing signal for clocking data on the TSDn pin is provided by the system side and shared by all eight framers, the Transmit System Interface should be set in Transmit Clock Slave mode. If the timing signal for clocking data on each TSDn pin is provided from each line side (processed timing signal), the Transmit System Interface should be set in Transmit Clock Master mode. In the Non-multiplexed Mode, if there is a common framing pulse provided by the system side for the eight framers, the Transmit System Interface should be set in Transmit Clock Slave mode. If there is not a common framing pulse, the Transmit System Interface should be set in Transmit Clock Master mode. In the Transmit Clock Slave mode, if the multi-function pin TSFSn/ TSSIGn is used to output the framing indication pulse, the Transmit System Interface is in Transmit Clock Slave TSFS Enable mode. If the TSFSn/TSSIGn is used to input the signaling bits to be inserted, the Transmit System Interface is in Transmit Clock Slave External Signaling mode. The T1/J1 mode E1 rate, which means the system clock rate is 2.048 MHz in T1/J1 mode, can only be supported in the Transmit Clock Slave mode. In the Transmit Clock Master mode, the multi-function pin TSFSn/ TSSIGn is used as TSFSn to input the framing indication pulse. Table - 33 summarizes the transmit system interface in different operation modes. To set the transmit system interface of each framer
into various operation modes, the registers must be configured as Table - 34. 3.13.2.1 Transmit Clock Slave Mode In the Transmit Clock Slave mode, the bit rate on the TSDn pin is 1.544 Mb/s. However, if the system clock rate is 2.048MHz, the data to be transmitted should be converted into the same rate as the line side, that is, to work in T1/J1 mode E1 rate. Thus the RATE[1:0] (b3~2, T1/J1005H) should be set to `01'. The conversion complies as follows: The last bit of the Frame N of the system side is the F-bit of the Frame N in the device. Then one byte of the system side is discarded after the previous three bytes are converted into the device. This process repeats eight times and the conversion of one frame is completed. Then the process goes on (refer to Figure - 51). In the Transmit Clock Slave mode, the Transmit Side System Common Clock B (TSCCKB) is provided by the system side. It is used as a common timing clock for all eight framers. The speed of the TSCCKB can be 1.544MHz or 2.048MHz. When it is 2.048MHz, the TSCCKB can be selected by the CMS (b5, T1/J1-015H) to be the same as the data (2.048Mb/S), or double the data (4.096Mb/s). The CMS (b5, T1/J1015H) of the eight framers should be set to the same value. If the speed of the TSCCKB is double of the data, there will be two active edges in one bit duration. In this case, the COFF (b4, T1/J1-015H) determines the active edge to sample the signal on the TSDn and TSSIGn pins and the active edge to update the pulse on the TSFSn pin; however, the pulse on the TSCFS is always sampled on its first active edge. In the Transmit Clock Slave mode, the Transmit Side System Common Clock A (TSCCKA) is provided by the system side. It is used as one of the reference clocks for the transmit jitter attenuator DPLL for all eight framers (refer to the Transmit Clock for details). In the Transmit Clock Slave mode, the Transmit Side System Common Frame Pulse (TSCFS) is used as a common framing signal to align
Table - 33. T1/J1 Mode Transmit System Interface in Different Operation Modes Operation Mode NonClock Slave TSFS Enable Multiplexed Mode External Signaling Mode Clock Master Mode Multiplexed Mode Data Pin TSDn TSDn TSDn MTSD Clock Pin TSCCKB TSCCKB LTCKn MTSCCKB Framing Pin TSCFS & TSFSn TSCFS TSFSn MTSCFS Signaling Pin No TSSIGn No MTSSIG Reference Clock TSCCKA TSCCKA TSCCKA & TSCCKB TSCCKA
Table - 34. Operation Mode Selection in T1/J1 Transmit Path
RATE[1:0] (b3~2, T1/J1-005H) 00 / 01 * 00 11 (in any of the eight framers) EMODE[1:0] (b7~6, T1/J1-005H) 10 11 01 11 Operation Mode Transmit Clock Slave TSFS Enable Transmit Clock Slave External Signaling Transmit Clock Master Transmit Multiplexed
Note: * When the RATE[1:0] are `00', the system clock rate is 1.544MHz. When the RATE[1:0] are `01', the system clock rate is 2.048MHz, i.e., T1/J1 mode E1 rate.
68
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
discarded the last bit 2.048M bit/s
discarded
discarded the last bit
TS0
TS1
TS2
TS3
TS4
TS5
TS6
TS31
TS0
TS2
1.544M bit/s
F
CH1
CH2
CH3
CH4
CH5
CH24
F
CH1
Figure - 51. E1 To T1/J1 Format Conversion data streams for the eight framers. The TSCFS is asserted on the request of each F-bit or the first F-bit of every 12 SFs / every 24 ESFs, which is indicated by the TSCFSP (b1, T1/J1-005H). The valid polarity of the TSCFS is configured by the FPINV (b5, T1/J1-005H). The Transmit Clock Slave Mode includes two sub-modes: Transmit Clock Slave TSFS Enable Mode and Transmit Clock Slave External Signaling Mode. Transmit Clock Slave TSFS Enable Mode 3.13.2.1.1 In this mode (refer to Figure - 35), the data on the system interface are clocked by the TSCCKB. The active edge of the TSCCKB to sample the pulse on the TSCFS and the data on the TSDn and TSFSn is determined by the following bits in the registers (refer to Table - 35). Figure - 52 to 54 show the functional timing examples. Bit 1 of each channel is the first bit to be transmitted. Table - 35. Active Edge Selection of TSCCKB (in T1/J1 Transmit Clock Slave TSFS Enable Mode)
the Bit Determining the Active Edge of the TSCCKB TSCFS TSD TSFS TSCCKBFALL (b3, T1/J1-004H) TSFSRISE (b5, T1/J1-004H)
Note: The TSCCKBFALL (b3, T1/J1-004H) of the eight framers should be set to the same value to ensure the TSCFS for the eight framers is sampled on the same active edge.
Besides all the common functions described in the Transmit Clock Slave mode, the special feature in this mode is that the multi-functional pin TSFSn/TSSIGn is used as TSFSn to output a framing pulse to indicate every F-bit.
The CMS (b5, T1/J1-015H) is logic 0. The bankplane rate is 1.544Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 1. TSCCKB TSCFS TSDn 1 2 3 4 5 CH24 (When the TSFSRISE (b5, T1/J1-004) is logic 0:) TSFSn (When the TSFSRISE (b5, T1/J1-004) is logic 1:) TSFSn 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5
Figure - 52. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 1
69
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b5, T1/J1-015H) is logic 0. The bankplane clock rate is 2.048Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 0. TSCCKB TSCFS TSDn
1
2
3
4
5 CH24
6
7
8
P
X
X
X
X
X
X
F
1
2
3
4 CH1
5
6
DUMMY
(When the TSFSRISE (b5, T1/J1-004) is logic 0:) TSFSn (When the TSFSRISE (b5, T1/J1-004) is logic 1:) TSFSn
Figure - 53. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 2
The CMS (b5, T1/J1-015H) is logic 1. The bankplane clock rate is 4.096Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 0. The COFF (b4, T1/J1-015H) is in its default value. TSCCKB TSCFS TSDn
1
2
3
4
5 CH24
6
7
8
P
X
X
X
X
X
X
F
1
2
3
4 CH1
5
6
DUMMY
(When the TSFSRISE (b5, T1/J1-004) is logic 0:) TSFSn (When the TSFSRISE (b5, T1/J1-004) is logic 1:) TSFSn
Figure - 54. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 3
70
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.13.2.1.2 Transmit Clock Slave External Signaling Mode In this mode (refer to Figure - 38), the data on the system interface are clocked by the TSCCKB. The active edge of the TSCCKB to sample the pulse on the TSCFS and the data on the TSDn and TSSIGn is determined by the TSCCKBFALL (b3, T1/J1-004H). The TSCCKBFALL (b3, T1/J1-004H) of the eight framers should be set to the same value to ensure the TSCFS for the eight framers is sampled on the same active edge.
Figure - 55 to 57 show the functional timing examples. Bit 1 of each channel is the first bit to be transmitted. Besides all the common functions described in the Transmit Clock Slave mode, the special feature in this mode is that the multi-functional pin TSFSn/TSSIGn is used as TSSIGn to input the signaling. The signaling on the TSSIGn pin may be configured by the ABXXEN (b4, T1/ J1-005H) to be valid only in the upper two-bit positions of the lower nibble of each channel (i.e. XXXXABXX) in T1 ESF mode.
The CMS (b5, T1/J1-015H) is logic 0. The bankplane rate is 1.544Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 0. TSCCKB TSCFS TSDn 1 2 3 4 5 CH24 TSSIGn X X X X A B C D X X X X 6 7 8 F 1 2 3 4 CH1 X X X X X X X 5 6 7 8 1 2 3 CH2 X X A 4 5
Figure - 55. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 1
The CMS (b5, T1/J1-015H) is logic 0. The bankplane rate is 2.048Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 1. TSCCKB TSCFS TSDn 1 2 3 4 5 CH24 TSSIGn X X X X A B C D P X X X 6 7 8 P X X X X X X F 1 2 3 4 CH1 X X X X X X A B 5 6
DUMMY X X
Figure - 56. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2
71
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b5, T1/J1-015H) is logic 1. The bankplane clock rate is 4.096Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 1. TSCCKB TSCFS TSDn 1 2 3 4 5 CH24 TSSIGn X X X X A B C D P X X X 6 7 8 P X X X X X X F 1 2 3 4 CH1 X X X X X X A B 5 6
DUMMY X X
Figure - 57. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 3
3.13.2.2 Transmit Clock Master Mode In the Transmit Clock Master mode (refer to Figure - 41), the Transmit Side System Common Clock A (TSCCKA) and Transmit Side System Common Clock B (TSCCKB) provided by the system side are used as one of the reference clocks for the transmit jitter attenuator DPLL for all eight framers (refer to the Transmit Clock for details). In the Transmit Clock Master mode, the multi-functional pin TSFSn/ TSSIGn is used as TSFSn to output a framing pulse to indicate every Fbit. In the Transmit Clock Master mode, the bit rate on the TSDn pin is 1.544Mb/s. In the Transmit Clock Master mode, each framer uses its own processed clock signal on LTCKn pin to sample/update the data on the system interface. The active edge of the LTCKn to sample the data on the TSDn pin is determinded by the TSDFALL (b1, T1/J1-004H). The active edge of the LTCKn to update the pulse on the TSFSn pin is determinded by the TSFSRISE (b5, T1/J1-004H). Figure - 58 shows the functional timing examples. Bit 1 of each channel is the first bit to be transmitted. 3.13.2.3 Transmit Multiplexed Mode In this mode (refer to Figure - 43), two multiplexed buses are used to input the data to all eight framers. Selected by the MTBS (b6, T1/J1015H) in each framer, the data on one of the two multiplexed buses is byte-interleaved input to up to four framers. When each four framers are selected, the input sequence of the data on the multiplexed bus is arranged by setting the channel offset TSOFF[6:0] (b6~0, T1/J1-014H). The data for a different framer from one multiplexed bus must be shifted by a different channel offset to avoid data mixing. Then the data on the multiplexed bus will be input to each of the four selected framers with a byte-interleaved manner. In the Transmit Multiplexed mode, the data on the system interface are clocked by the MTSCCKB. The active edge of the MTSCCKB to sample the data on the MTSCFS, MTSD and MTSSIG is determined by the TSCCKBFALL (b3, T1/J1-004H). The TSCCKBFALL (b3, T1/J1004H) of the eight framers should be set to the same value. In the Transmit Multiplexed mode, the Multiplexed Transmit Side Sys72
tem Common Clock B (MTSCCKB) is provided by the system side. It is used as a common timing clock for all eight framers. The speed of the MTSCCKB can be selected by the CMS (b5, T1/J1-015H) to be the same as the data to be transmitted (8.192MHz), or double the data (16.384MHz). If the speed of the MTSCCKB is double the data to be transmitted, there will be two active edges in one bit duration. In this case, the COFF (b4, T1/J1-015H) determines the active edge to sample the signal on the MTSD and MTSSIG pins and the active edge to update the pulse on the MTSFS pin; however, the pulse on the MTSCFS is always sampled on its first active edge. If the CMS (b5, T1/J1-015H) or the COFF (b4, T1/J1-015H) of any of the eight framers is configured as logic 1, all the others are taken as logic 1. That is, the CMS (b5, T1/J1015H) and the COFF (b4, T1/J1-015H) of the eight framers should be configured to the same value in the Transmit Multiplexed mode. In the Transmit Multiplexed mode, the Transmit Side System Common Clock A (TSCCKA) is provided by the system side. It is used as one of the reference clocks for the transmit jitter attenuator DPLL for all eight framers (refer to the Transmit Clock for details). In the Transmit Multiplexed mode, the Multiplexed Transmit Side System Common Frame Pulse (MTSCFS) is used as a common framing signal to align data streams on the two multiplexed buses. The MTSCFS is asserted on the F-bit of the selected first framer. The valid polarity of the MTSCFS is congifured by the FPINV (b5, T1/J1-005H). The FPINV (b5, T1/J1-005H) of the eight framers should be the same value. In the Transmit Multiplexed mode, the bit rate on the MTSD pin is 8.192Mb/s. In the Transmit Multiplexed mode, the MTSSIG input the signaling bits to be inserted. The signaling bits are channel aligned with the data input from the MTSD. The signaling on the MTSSIG pin may be configured by the ABXXEN (b4, T1/J1-005H) to be valid only in the upper two-bit positions of the lower nibble of each channel (i.e. XXXXABXX) in T1 ESF mode. Figure - 59 ~ 60 show the functional timing examples. Bit 1 of each channel is the first bit to be transmitted.
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
LTCKn is 1.544M LTCKn When the TSFSRISE (b5, T1/J1-004H) is logic 1 and the TSDFALL (b1, T1/J1-004) is logic 1: TSFSn TSDn 1 2 3 4 5 CH24 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5
When the TSFSRISE (b5, T1/J1-004H) is logic 0 and the TSDFALL (b1, T1/J1-004) is logic 0: TSFSn TSDn 1 2 3 4 5 CH24 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5
When the TSFSRISE (b5, T1/J1-004H) is logic 0 and the TSDFALL (b1, T1/J1-004) is logic 1: TSFSn TSDn 1 2 3 4 5 CH24 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5
When the TSFSRISE (b5, T1/J1-004H) is logic 1 and the TSDFALL (b1, T1/J1-004) is logic 0: TSFSn TSDn 1 2 3 4 5 CH24 6 7 8 F 1 2 3 4 CH1 5 6 7 8 1 2 3 CH2 4 5
Figure - 58. T1/J1 Transmit Clock Master Mode - Functional Timing Example
73
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The CMS (b5, T1/J1-015H) is logic 0, i.e., the bankplane rate is 8.192Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 1. In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus. The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF[2:0] of the four Framers are set to logic 0: MTSCFS MTSCCKB 8 P Parity bit MTSSIG D P X X X X X X X F P X X X F P X X X X F P X X X X 3 6 7
MTSD
X
X
X
X
X
X
X
X
F F-bit
1
2
4
5
8
Framer1 X X X X
Parity F-bit bit X P X X
Framer2 X X X X
Parity F-bit bit X P X X
Framer3 X X X X
F-bit Parity bit X P X X
Framer4 X X X X
Framer1_CH1 X X X X A B C D
X
Line Interface (of any of the Framer1 to Framer4). LTCKn is 1.544M: LTCKn LTDn CH24-7 CH24-8 F CH1-1 CH1-2 CH1-3 CH1-4 CH1-5
Figure - 59. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 1
The CMS (b5, T1/J1-015H) is logic 1, i.e., the bankplane clock rate is 16.384Mbit/s. The TSCCKBFALL (b3, T1/J1-004H) is logic 0. In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus. The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF of the four Framers are set to logic 0: MTSCFS MTSCCKB 8 P Parity bit MTSSIG D P X X X X X X F P X X X F P X X X X F P X X X X 3 6 7
MTSD
X
X
X
X
X
X
X
X
X
F F-bit
1
2
4
5
8
Framer1 X X X X
Parity F-bit bit X P X X
Framer2 X X X X
Parity F-bit bit X P X X
Framer3 X X X X
F-bit Parity bit X P X X
Framer4 X X X X
Framer1_CH1 X X X X A B C D
X
Line Interface (of any of the Framer1 to Framer4). LTCK is 1.544M: LTCKn
LTDn
CH24-7
CH24-8
F-bit
CH1-1
CH1-2
CH1-3
CH1-4
CH1-5
Figure - 60. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 2
74
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.13.2.4 Parity Check In the above four modes, parity check is calculated over the bits in the previous frame and the result is input into the F-bit on the TSDn/MTSD and TSSIGn/MTSSIG pin. The even parity or odd parity is selected by the TPTYP (b7, T1/J1-002H) and whether the F-bit is calculated or not is determined by the PTY_EXTD (b3, T1/J1-002H). The parity error event on the TSDn pin will be captured by the TSDI (b5, T1/J1-002H) and the parity error event on the TSSIGn pin will be captured by the TSSIGI (b4, T1/J1-002H). The TSDI (b5, T1/J1-002H) and TSSIGI (b4, T1/J1-002H) will be cleared after being read. The parity error will cause an interrupt on the INT pin if the TPRTYE (b6, T1/J1-002H) is enabled. 3.13.2.5 Offset When the system clock rate is 2.048MHz (in Transmit Clock Slave T1/J1 mode E1 rate mode) or 8.192MHz (in Transmit Multiplexed mode), the channel offset and/or bit offset between the TSCFS/MTSCFS and
the start of the corresponding frame on the TSDn/MTSD can be configured. The channel offset and bit offset can be set in both single clock mode (CMS [b5, T1/J1-015H] = 0) and double clock mode (CMS [b5, T1/J1-015H] = 1). The channel offset is enabled by setting a non-zero value into the TSOFF[6:0] (b6~0, T1/J1-014H). The TSOFF[6:0] (b6~0, T1/J1-014H) give a binary representation. The bit offset is enabled by setting a non-zero value into the BOFF[2:0] (b2~0, T1/J1-015H). The bit offset value equals the setting in the BOFF[2:0] (b2~0, T1/J1-015H). That is, `000' in the BOFF[2:0] (b2~0, T1/J1-015H) means no bit offset; `001' in the BOFF[2:0] (b2~0, T1/J1-015H) means one bit offset, and so on (refer to the examples in Figure - 61 and Figure - 62). When the bit offset is configured, the signal on the TSSIGn/MTSSIG or the pulse on the TSFSn is aligned to the RSDn/MRSD.
For example: in Transmit Clock Slave mode, CMS (b5, T1/J1-015H) = 0, TSCCKBFALL (b3, T1/J1-004H) = 1: TSCFS TSCCKB The bit offset is 0: TSDn 1 2 3 4 CH24 5 6 7 8 P X X X X X X F 1 2 3 CH1 4
DUMMY
The bit offset is set as: BOFF[2:0] (b2~0, E1-01CH) = 010; i.e. 2-bit offset: TSDn 1 2 3 4 CH24 5 6 7 8 P X X X X X X F 1 2 3 CH1 4
DUMMY
Figure - 61. Transmit Bit Offset in T1/J1 Mode - 1
For example: in Transmit Clock Slave mode, CMS (b5, T1/J1-015H) = 1, TSCCKBFALL (b3, T1/J1-004H) = 0: TSCFS TSCCKB The bit offset is 0: TSDn 1 2 3 4 5 6 7 8 P X X X X X X F 1 2 3 CH1 4
CH24
DUMMY
The bit offset is set as: BOFF[2:0] (b2~0, E1-01CH) = 011; i.e. 3-bit offset: TSDn 1 2 3 4 5 6 7 8 P X X X X X X F 1 2 3 CH1 4
CH24
DUMMY
Figure - 62. Transmit Bit Offset in T1/J1 Mode - 2
75
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.14 TRANSMIT PAYLOAD CONTROL (TPLC)
Different test patterns can be inserted in the data to be transmitted or the data to be transmitted can be extracted to the PRBS Generator/Detector for test in this block. The Transmit Payload Control of each framer operates independently. 3.14.1 E1 MODE To enable the test for the data to be transmitted, the PCCE (b0, E1060H) must be set to activate the setting in the indirect registers (from 20H to 7FH of TPLC indirect registers). The following methods can be used for test on a per-TS basis: - Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the data to be transmitted on one of the eight framers will be extracted to the PRBS Generator/Detector when the RXPATGEN (b2, E1-00CH) is 1. The data can be extracted in framed or unframed mode. The selection is made by the UN_DET (b0, E1-00CH). In unframed mode, all 32 timeslots are extracted and the per-timeslot configuration in the TEST (b3, E1-TPLC-indirect registers - 20~3FH) is ignored. In framed mode, the data to be transmitted will only be extracted on the timeslot configured by the TEST (b3, E1-TPLC-indirect registers - 20~3FH). Refer to the section of PRBS GENERATOR / DETECTOR (PRGD) for details. - Enable the payload loopback by setting the LOOP (b2, E1-TPLC-indirect registers - 20~3FH) (refer to Payload Loopback). - Replace the data input from the TSDn/MTSD pin with the -law or A-law milliwatt pattern (refer to Table - 8 & Table - 9) when the SUBS (b7, E1-TPLC-indirect registers - 20~3FH), the DS0 (b4, E1-TPLC-indirect registers - 20~3FH) and the DS1 (b5, E1-TPLC-indirect registers 20~3FH) are logic 1,1,1 or 1,1,0 respectively. - Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the test pattern from the PRBS Generator/Detector will replace the data input from the TSDn/MTSD pin of one of the eight framers when the RXPATGEN (b2, E1-00CH) is 0. The test pattern can replace the data in framed or unframed mode. The selection is made by the UN_GEN (b1, E1-00CH). In unframed mode, all the 32 timeslots are replaced and the per-timeslot configuration in the TEST (b3, E1-TPLC-indirect registers - 20~3FH) is ignored. In framed mode, the received data will only be replaced on the timeslot configured by the TEST (b3, E1-TPLC-indirect registers 20~3FH). Refer to the section of PRBS GENERATOR / DETECTOR (PRGD) for details. - Replace the data input from the TSDn/MTSD pin with the value in the IDLE[7:0] (b7~0, E1-TPLC-indirect registers - 40~5FH) when the SUBS (b7, E1-TPLC-indirect registers - 20~3FH) and the DS0 (b4, E1TPLC-indirect registers - 20~3FH) are logic 1,0. - Invert the odd bits, even bits or all bits input from the TSDn/MTSD pin when the SUBS (b7, E1-TPLC-indirect registers - 20~3FH), the DS0 (b4, E1-TPLC-indirect registers - 20~3FH) and the DS1 (b5, E1-TPLCindirect registers - 20~3FH) are logic 0,0,1 or 0,1,0 or 0,1,1 respectively. (The above methods are arranged from highest to lowest in priority.) - Replace the signaling input from the TSSIGn pin with the value in the A, B, C, D (b3~0, E1-TPLC-indirect registers - 61~7FH) with the SIGSRC (b4, E1-TPLC indirect registers - 61~7FH) being logic 1 when the Channel Associated Signaling (CAS) is selected by the SIGEN (b6, E1-040H) & DLEN (b5, E1-040H). Addressed by the A[6:0] (b6~0, E1-062H), the data read from or written into the indirect registers are in the D[7:0] (b7~0, E1-063H). The read or write operation is determined by the R/WB (b7, E1-062H). The indirect registers have a read/write cycle. Before the read/write operation is com-
pleted, the BUSY (b7, E1-061H) will be set. New operations on the indirect registers can only be implemented when the BUSY (b7, E1-061H) is cleared. The read/write cycle is 490ns. 3.14.2 T1 / J1 MODE To enable the test for the data to be transmitted, the PCCE (b0, T1/ J1-030H) must be set to activate the setting in the indirect registers (from 01H to 48H of TPLC indirect registers). The following methods can be executed for test on a per-channel basis: - Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the data to be transmitted on one of the eight framers will be extracted to the PRBS Generator/Detector when the RXPATGEN (b2, T1/J1-00FH) is 1. The data can be extracted in framed or unframed mode. The selection is made by the UN_DET (b0, T1/J1-00FH). In unframed mode, all 24 channels and the F-bit are extracted and the per-channel configuration in the TEST (b3, T1/J1-TPLC-indirect registers - 01~18H) is ignored. In framed mode, the data to be transmitted will only be extracted on the channel specified by the TEST (b3, T1/J1-TPLC-indirect registers - 01~18H). Fractional T1/J1 data can also be extracted in the specified channel when the Nx56k_DET (b3, T1/J1-00FH) is set. Refer to the section of the PRBS GENERATOR / DETECTOR (PRGD) for details. - Enable three types of Zero Code Suppression when the ZCS[1:0] (b1~0, T1/J1-TPLC-indirect registers - 01~18H) is configured. - Enable the payload loopback by setting the LOOP (b2, T1/J1-TPLCindirect registers - 01~18H) (refer to Payload Loopback). - Replace the data input from the TSDn/MTSD pin with the milliwatt pattern when the DMW (b5, T1/J1-TPLC-indirect registers - 01~18H) is logic 1. (The milliwatt is -law. Refer to Table - 9.) - Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the test pattern from the PRBS Generator/Detector will replace the data input from the TSDn pin of one of the eight framers when the RXPATGEN (b2, T1/J100FH) is 0. The test pattern can replace the data in framed of unframed mode. The selection is made by the UN_GEN (b1, T1/J1-00FH). In unframed mode, all the 24 channels and the F-bit are replaced and the per-channel configuration in the TEST (b3, T1/J1-TPLC-indirect registers - 01~18H) is ignored. In framed mode, the received data will only be replaced on the channel specified by the TEST (b3, T1/J1-TPLC-indirect registers - 01~18H). Fractional T1/J1 signal can also be replaced in the specified channel when the Nx56k_GEN (b4, T1/J1-00FH) is set. Refer to the section of PRBS GENERATOR / DETECTOR (PRGD) for details. - Replace the data input from the TSDn/MTSD pin with the value in the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers - 19~30H) when the IDLE_DS0 (b6, T1/J1-TPLC-indirect registers - 01~18H) is set. - Invert the most significant bit and/or the other bits in a channel input from the TSDn pin when the SIGNINV and the INVERT (b4 & b7, T1/J1TPLC-indirect registers - 01~18H) is set. (The above methods are arranged from highest to lowest in priority.) - Replace the signaling input from the TSSIGn pin with the value in the A, B, C, D (b3~0, T1/J1-TPLC-indirect registers - 31~48H) when the SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers - 31~48H) is configured. The data of all channels can be selected by the GZCS[1:0] (b1~0, T1/ J1-044H) to be in GTE and Bell Zero Code Suppression when the bits in a channel are all zeros. The setting in the GZCS[1:0] (b1~0, T1/J1-044H) are logically ORed with the setting in the ZCS[1:0] (b1~0, T1/J1-TPLCindirect registers - 01~18H). Addressed by the A[6:0] (b6~0, T1/J1-032H), the data read from or written into the indirect registers are in the D[7:0] (b7~0, T1/J1-033H).
76
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
The read or write operation is determined by the R/WB (b7, T1/J1032H). Before the read/write operation is completed, the BUSY (b7, T1/ J1-031H) will be set. New operations on the indirect registers can only be implemented when the BUSY (b7, T1/J1-031H) is cleared The read/ write cycle is 650ns.
setting will only substitute the IDLE code for the TS1~15 and TS17~31. The TS16 is occupied by signaling. However, the MTRK (b7, E1-041H) takes effect only when the PCCE (b0, E1-060H) in the Transmit Payload Control is logic 1. Alarm Indication When special conditions occurs in the received data stream, alarm indication will be transmitted automatically. The alarm indication can also be transmitted manually. A logic 1 in the 3rd bit of NFAS (A bit) is the Remote Alarm Indication (RAI) signal. It is controlled by the REMAIS (b3, E1-041H), the AUTOYELLOW (b3, E1-000H) and the G706RAI (b0, E1-00EH) as illustrated in Table - 36. When CRC-4 Multi-Frame is generated, the international bits of frame 13 & 15 (E1 & E2 bits) are used for FEBE indication only if the FEBEDIS (b2, E1-040H) is logic 0. When there are CRC calculated errors in SMF I or SMF II in the received data stream, a logic 0 will be automatically replaced in the E1 or the E2 bit for indication respectively. When the received data are out of CRC-4 Multi-Frame synchronization, the E1 and E2 bits can be forced to be logic 0 or logic 1, which is selected by the OOCMFE0 (b1, E1-00EH). When Signaling Multi-Frame is generated, the 6th bit of TS16 of frame 0 (Y bit) is for Signaling Multi-frame Alarm Indication. A logic 1 in the Y bit means the Signaling Multi-frame Alarm. However, the value of the Y bit can be forced to be logic 0 or logic 1 by the MFAIS (b2, E1041H). Control Over International / National / Extra Bits After the Basic Frame is generated, the international bits (the first bit in TS0) can be replaced with the INDIS (b1, E1-040H) being logic 0. The setting in the Si[1:0] (b7~6, E1-042H), the CRC-4 Multi-Frame and FEBE signal can all replace the international bits. Their priorities are controlled by the GENCRC (b4, E1-040H) and the FEBEDIS (b2, E1040H) and illustrated in Table - 37. When the setting in the SaX[1:4] (b3~0, E1-047H) is activated by the corresponding SaX_EN[1:4] (b7~4, E1-047H), it will replace the data on the national bits whose position is selected by the SaSEL[2:0] (b7~5, E1046H). When Signaling Multi-Frame is generated, the extra bits (bits 4, 6 & 7 in TS16 of frame 0 of the Signaling Multi-Frame) can be replaced with the setting in the X[2:0] (b0~1 & b3, E1-043H) if the XDIS (b0, E1-040H) is logic 0.
3.15 FRAME GENERATOR (FRMG)
The Frame Generator of each framer operates independently. 3.15.1 E1 MODE In E1 mode, the Frame Generator can generate Basic Frame, CRC-4 Multi-Frame and Channel Associated Signaling (CAS) Multi-Frame. The Frame Generator can also transmit alarm indication signal when special conditions occurs in the received data stream. International bits, National bits and Extra bits replacement and data invertion are all supported in the Frame Generator. Generation In E1 mode, the data to be transmitted can be formed to be Basic Frame, CRC-4 Multi-Frame and Signaling Multi-Frame. The Basic Frame is generated when the FDIS (b3, E1-040H) is logic 0. The Basic Frame alignment sequence (FAS) - X0011011 will replace the data on the TS0 of each even frame and a logic 1 should be fixed in the 2nd bit of each odd frame. The CRC-4 Multi-Frame is generated by setting the GENCRC (b4, E1-040H) when the INDIS (b1, E1-040H) is logic 0. The CRC-4 MultiFrame alignment pattern - 001011 will replace the data on the international bits of the odd basic frames 1~11, and the calculated CRC bits will replace the data on the international bits of the even Basic Frames. The CRC bits are calculated every Sub Multi-Frame (SMF) and located in the next SMF. If the data input from the TSDn pin have already been in CRC Multi-Frame format, the CRC bits can be modified by setting the PATHCRC (b4, E1-002H) to transmit the CRC-4 transparently or modify the CRC-4 bits. The Signaling Multi-Frame is generated by setting the SIGEN (b6, E1-040H) & the DLEN (b5, E1-040H) to logic 1 (CAS enable). The Signaling Multi-Frame alignment pattern - 0000 will replace the higher nibble (b1 ~ b4) of the TS16 of Basic Frame 0, and the signaling source selected by the SIGSRC (b4, E1-TPLC-indirect registers - 61~7FH) will replace the data on TS16 of Basic Frame 1~15 (refer to Transmit Payload Control). When the Signaling Multi-Frame is not generated, setting a logic one in the MTRK (b7, E1-041H) will substitute the IDLE code set in the IDLE[7:0] (b7~0, E1-TPLC-indirect registers - 40~5FH) for all the data on the TS1~31. When the Signaling Multi-Frame is generated, the
Table - 36. Remote Alarm Indication
REMAIS (b3, E1-041H) 1 0 0 AUTOYELLOW (b3, E1-000H) 1 1 0 G706RAI (b0, E1-00EH) 0 Remote Alarm Indication Signal Manually force the remote alarm indication signal to be logic 1. (per ETSI) The RAI is transmitted in any of the four conditions occurred in the received data stream: 1. out of Basic Frame; 2. during AISD; 3. in CRC-4 to non-CRC-4 interworking; 4. the offline searching is out of Basic Frame sync. (per Annex B of G.706) The RAI is transmitted in any of the two conditions occurred in the received data stream: 1. out of Basic Frame; 2. during AISD. The RAI is not transmitted, that is, logic 0 is forced to transmit in its position.
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Table - 37. Content in International Bits (when the INDIS [b1, E1-040H] is logic 0)
GENCRC (b4, E1-040H) 0 1 1 FEBEDIS (b2, E1-040H) 0 1 The Data on the International Bits The international bits of the FAS frame represent the setting in the Si[1] (b7, E1-042H), while the international bits of the NFAS frame represent the setting in the Si[0] (b6, E1-042H). The international bits of the FAS frame represent the calculated CRC-4 bits; the international bits of the former six NFAS frames represent the CRC-4 alignment sequence (001011). The other two international bits in frame 13 & 15 represent whether there are CRC-4 calculated errors in the received data stream (FEBE). The international bits of the FAS frame represent the calculated CRC-4 bits; the international bits of the former six NFAS frames represent the CRC-4 alignment sequence (001011). The other two international bits in frame 13 & 15 represent the setting in the Si[1:0] (b7~6, E1-042H) respectively.
Diagnostics For diagnostic purposes, three kinds of data invertion can be executed: 1. When Basic Frame is generated, the FAS can be inverted from `0011011' to `1100100' by setting the FPATINV (b6, E1-041H); 2. When Basic Frame is generated, the 2nd bit of the NFAS can be inverted from `1' to `0' by setting the SPLRINV (b5, E1-041H); 3. When Signaling Multi-Frame is generated, the Signaling MultiFrame alignment pattern can be inverted from `0000' to `1111' by setting the SPATINV (b4, E1-041H). Of all the operations, transmitting all ones take the highest priority. All ones can be transmitted only in TS16 when the TS16AIS (b1, E1-041H) is set. All ones can also be transmitted on all the timeslots when the AIS (b0, E1-041H) is set. A FIFO is employed in the Frame Generator to store the data stream to be transmitted. The FIFO can be initiated by setting the FRESH (b7, E1-040H). Interrupt Summary The interrupt sources are summaried in Table - 38. When the conditions are met, the corresponding Interrupt Status bit will be logic 1. Then the interrupt will occur on the INT pin if the Interrupt Enable bit is logic 1. 3.15.2 T1 / J1 MODE In T1/J1 mode, the data to be transmitted can be either the Super Frame (SF) or the Extended Super Frame (ESF) format. The selection is made by the ESF (b4, T1/J1-044H). The SF/ESF is generated on the base of the UF (b6, T1/J1-046H) Table - 38. Interrupt Summary
No. 1 2 3 4
and the FDIS (b3, T1/J1-006H) are logic 0, that is, the F-bit can be replaced with the Frame Alignment Pattern, DL and CRC-6 (the DL and CRC-6 bits only exist in the ESF format). Thus, the FAS can be replaced in its position when the FBITBYP (b2, T1/J1-006H) is logic 0. In SF format, the Frame Alignment Pattern is `10001101110X' and replaces the Fbit of each frame input from the TSDn pin (refer to Table - 3). In ESF format, the Frame Alignment Pattern is `001011' and replaces the F-bit in every 4th frame starting with Frame 4. The CRC-6 can replace the F-bit in every 4th frame starting with Frame 2 if the CRCBYP (b1, T1/J1006H) is logic 0. The CRC-6 algorithm is selected between the T1 standard and the J1 standard by the J1_CRC (b6, T1/J1-044H). The DL bits will replace the F-bit in every other frame starting with Frame 1 when the FDLBYP (b0, T1/J1-006H) is logic 0 (refer to Table - 4). Before the data coming into the Frame Generator, if the SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers - 31~48H) select the signaling bit input from the TSDn pin to be replaced with the signaling input from the TSSIGn pin, the signaling bit of all channels can be replaced with the signaling of the 1st frame when the SIGAEN (b5, T1/J1-006H) is set. This configuration is to avoid the signaling change in the middle of a SF/ ESF. The data input from the TSDn pin will be replaced by the code set in the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers - 19~30H) when the MTRK (b7, T1/J1-044H) is set. When the MTRK (b7, T1/J1-044H) is set, the signaling bits of all channels may also be replaced by the signaling input from the TSSIGn pin or the data set in the A, B, C, D (b3~0, T1/J1TPLC-indirect registers - 31~48H) according to the setting in the SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers - 31~48H). The MTRK (b7, T1/J1-044H) takes effect only when the PCCE (b0, T1/J1-030H) in
Interrupt Sources The end of the first frame of a Signaling Multi-Frame is input to the Frame Generator when Signaling Multi-Frame is generated and coincides with the CRC Multi-Frame. The end of the first frame of a CRC-4 Multi-Frame is input to the Frame Generator when CRC Multi-Frame is generated. The end of the first frame of a CRC-4 Sub Multi-Frame is input to the Frame Generator when CRC Multi-Frame is generated. The boundary of a FAS is input to the Frame Generator when Basic Frame is generated.
Indication Bits SIGMFI (b4, E1-045H) MFI (b2, E1-045H) SMFI (b1, E1-045H) FASI (b3, E1-045H)
Interrupt Mask Bits SIGMFE (b4, E1-044H) MFE (b4, E1-044H) SMFE (b4, E1-044H) FASE (b4, E1-044H)
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the TPLC is logic 1. Configured by the TXMFP (b1, T1/J1-00AH), the mimic pattern can be inserted in the 1st bit of each channel. The content of the mimic pattern is the same as the F-bit. The mimic pattern insertion is for diagnostic purposes. The Yellow alarm signal can be inserted in the data stream to be transmitted when the XYEL (b2, T1/J1-045H) is enabled. The alarm signal pattern is selected between the T1 and J1 mode by the J1_YEL (b5, T1/J1-044H). The pattern is: - In T1 SF format: Transmit the logic 0 on the 2nd bit of each channel. - In J1 SF format: Transmit the logic 1 on the 12th F-bit. - In T1 ESF format: Transmit the `FF00' on each DL of F-bit. - In J1 ESF format: Transmit the `FFFF' on each DL of F-bit. The Yellow alarm signal can also be inserted automatically by setting the AUTOYELLOW (b3, T1/J1-000H) when Red alarm is declared in the received data stream. In ESF format, if the Yellow alarm signal is stopped by setting the XYEL (b2, T1/J1-045H) to be logic 0, a Yellow alarm disabled pattern will be transmitted automatically. In T1 mode, the pattern is `FFFF'. In J1 mode, the pattern is `FF7E'. The disable pattern should be repeated 16 times before the BOC (refer to Bit-Oriented Message Transmitter) or the HDLC bits (refer to HDLC Transmitter) are inserted in the DL bit. The Yellow alarm takes the highest priority in these three kinds of insertion. If there are no Yellow alarm signal, no BOC, no HDLC bits or noTPLC insertion in the DL of the F-bit, the DL position will be forced to transmit `FFFF' in T1 mode or `7E7E' in J1 mode continuously. A FIFO is employed in the Frame Generator to store the data stream to be transmitted. The FIFO can be initiated by setting the FRESH (b7, T1/J1-006H).
3.16 HDLC TRANSMITTER (THDLC)
The HDLC data insertion is performed in this block. The HDLC Transmitters #1, #2 and #3 in E1 mode or the HDLC Transmitter #1 and #2 in T1/J1 mode ESF format of each framer operate independently. 3.16.1 E1 MODE Three HDLC Transmitter blocks are provided for each framer to transmit a HDLC link. Before selecting the HDLC link, the TXCISEL (b3, E10AH) should be set to 1. Thus, the congifuration of Link Control and Bits Select registers (addressed from 028H to 02DH) is for THDLC. The THDLCSEL[1:0] (b5~4, E1-00AH) select one of the three HDLC controllers to be accessed by the microcontroller. The #2 and #3 blocks can also be disabled by setting the V52DIS (b3, E1-007H). The functionality of the HDLC link can be defined as the follows: 1. Set the DL_EVEN (b7, E1-028H or b7, E1-02AH or b7, E1-02CH) and/or the DL_ODD (b6, E1-028H or b6, E1-02AH or b6, E1-02CH) to select the even and/or odd frames (the even frames are FAS frames while the odd frames are NFAS frames); 2. Set the DL_TS[4:0] (b4~0, E1-028H or b4~0, E1-02AH or b4~0, E1-02CH) to select the timeslot of the assigned frame or to select the TS16_EN (b5, E1-028H) to define the TS16 of the assigned frame (this HDLC link can only be set in the #1 block and is enabled when the CCS is selected by the SIGEN [b6, E1-040H] and the DLEN [b5, E1-040H]); 3. Set the DL_BIT[7:0] (b7~0, E1-029H or b7~0, E1-02BH or b7~0, E1-02DH) to select the bit of the assigned timeslot. Thereafter, the HDLC packet will replace the data on the assigned data link. All the functions of the selected HDLC Transmitter block can
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be realized only if the EN (b0, E1-050H) is set to logic 1; otherwise, all ones will be transmitted on the assigned data link. A normal HDLC packet (refer to Figure - 3) is started with a 7E (Hex) flag, then the HDLC data are transmitted. Before closing, two bytes of CRC-CCITT frame check sequences (FCS) are added if the CRC (b1, E1-050H) is enabled. The HDLC packet is closed with another 7E flag. However, if the FLGSHARE (b7, E1-050H) is set, the closing flag of the current HDLC packet and the opening flag of the next HDLC packet are shared. A FIFO buffer is used to store the HDLC data written to the TD[7:0] (b7~0, E1-055H). The UTHR[6:0] (b6~0, E1-051H) sets the upper threshold of the FIFO. When the data exceed the fill level, the data will be transmitted. The opening flag will be prepended before the data automatically. The transmission won't stop until the entire HDLC data are transmitted and the data in the FIFO are below the upper threshold. The end of the current entire HDLC frame is set by the EOM (b3, E1-050H). When it is set, the HDLC data should be transmitted even if they don't exceed the upper threshold of the FIFO. The FCS, if enabled, will be added before the closing flag automatically. Zero stuffing is automatically performed to the serial output data when there are five consecutive ones in the HDLC data or in the FCS. A 7F (Hex) abort sequence which deactivates the current HDLC packet can be inserted anytime the ABT (b2, E1-050H) is set. When the ABT (b2, E1-050H) is set, the current byte in the TD[7:0] (b7~0, E1-055H) is still transmitted, and then the FIFO is cleared and the 7F abort sequence is transmitted continuously. The low threshold of the FIFO can be set in the LINT[6:0] (b6~0, E1-052H), which should always be less than the value of the UTHR[6:0] (b6~0, E1051H). The FIFO can be cleared anytime the FIFOCLR (b6, E1-050H) is set. Flags (7E) will consecutively be transmitted when there is no HDLC data to be transmitted if the data link is activated. Four interrupt sources can be derived from this block. 1. When the data in the FIFO is empty or less than the setting in the LINT[6:0] (b6~0, E1-052H), the BLFILL (b5, E1-054H) will indicate. A transition from logic 0 to 1 on the BLFILL (b5, E1-054H) will cause a logic 1 in the LFILLI (b0, E1-054H). The interrupt on the INT pin will occur when the LFILLE (b0, E1-053H) is enabled; 2. When the data in the FIFO reach its maximum capacity - 128 bytes, the FULL (b6, E1-054H) will be set for indication. A transition from logic 0 to 1 on the FULL (b6, E1-054H) will cause a logic 1 in the FULLI (b3, E1-054H). The interrupt on the INT pin will occur when the FULLE (b3, E1-053H) is enabled; 3. When the FIFO has already been filled with 128 bytes and new data are still written to it, the FIFO will overflow and the OVRI (b2, E1054H) will be set for indication. The interrupt on the INT pin will occur when the OVRE (b2, E1-053H) is enabled. 4. When the transmission is in process and it is out of data to be transmitted in the FIFO, the FIFO is underrun and the UDRI (b1, E1054H) will be set for indication. The interrupt on the INT pin will occur when the UDRE (b1, E1-053H) is enabled. 3.16.2 T1 / J1 MODE In the SF format, there is no HDLC link. In the ESF format, two HDLC Transmitter blocks (#1 and #2) are employed for each framer to transmit the HDLC link. Before selecting the HDLC link, the TXCISEL (b3, T1/J1-00DH) should be set to 1. Thus, the configuration of the Link Control and Bits Select registers (addressed from 070H to 071H) is for THDLC. Selected by the THDLCSEL[1:0]
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(b5~4, T1/J1-00DH), registers in one of the two HDLC Transmitter blocks are accessable to the microprocessor. The #1 block transmits the HDLC link in the DL of F-bit (its position is shown in the Table - 4). The #2 block transmits the HDLC link in a channel and its position is selected as follows: 1. Set the DL2_EVEN (b7, T1/J1-070H) and/or the DL2_ODD (b6, T1/J1-070H) to select the even and/or odd frames; 2. Set the DL2_TS[4:0] (b4~0, T1/J1-070H) to select the channel of the assigned frame; 3. Set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to select the bit of the assigned channel. All the functions of the selected HDLC Transmitter block can be realized only if the EN (b0, T1/J1-034H) is enabled; otherwise, all ones will be transmitted on the assigned data link. The structure of the HDLC packet (refer to Figure - 3) is the same as it is described in the E1 mode. When the FLGSHARE (b7, T1/J1-034H) is set, the closing flag of the current HDLC and the opening flag of the next HDLC is shared. A FIFO buffer is used to store the HDLC data written to the TD[7:0] (b7~0, T1/J1-039H). The UTHR[6:0] (b6~0, T1/J1-035H) limit the upper threshold of the FIFO. When the data exceed the fill level, the data will be transmitted. The opening flag will be added before the data automatically. The transmission won't stop until an entire HDLC frame is transmitted and the data in the FIFO is below the upper threshold. The end of the current entire HDLC frame is indicated by the EOM (b3, T1/J1034H). When it is set, the HDLC data should be transmitted even if it does not exceed the upper threshold of the FIFO. The FCS, if enabled by the CRC (b1, T1/J1-034H), will be added before the closing flag automatically. Zero stuffing is automatically performed to the serial output data when there are five consecutive ones in the HDLC data or in the FCS. A 7F abort sequence which deactivates the current HDLC packet can be inserted anytime the ABT (b2, T1/J1-034H) is set. When the ABT (b2, T1/J1-034H) is set, the current byte in the TD[7:0] (b7~0, T1/J1039H) is still transmitted, and then the FIFO is cleared and the 7F abort sequence is transmitted continuously. The low threshold of the FIFO can be set in the LINT[6:0] (b6~0, T1/J1-036H), which should always be less than the value of the UTHR[6:0] (b6~0, T1/J1-035H). The FIFO can be cleared anytime the FIFOCLR (b6, T1/J1-034H) is set. Flags (7E) will consecutively be transmitted when there is no HDLC data to be transmitted during the data link activating. Four interrupt sources can be derived from this block. 1. When the FIFO is empty or the data in the FIFO is less than the setting in the LINT[6:0] (b6~0, T1/J1-036H), the BLFILL (b5, T1/J1-038H) will be set for indication. A transition from logic 0 to 1 on the BLFILL (b5, T1/J1-038H) will cause a logic 1 in the LFILLI (b0, T1/J1-038H). The interrupt on the INT pin will occur when the LFILLE (b0, T1/J1-037H) is enabled; 2. When the data in the FIFO reach its maximum capacity - 128 bytes, the FULL (b6, T1/J1-038H) will be set for indication. A transition from logic 0 to 1 on the FULL (b6, T1/J1-038H) will cause a logic 1 in the FULLI (b3, T1/J1-038H). The interrupt on the INT pin will occur when the FULLE (b3, T1/J1-037H) is enabled; 3. When the FIFO has been filled with 128 bytes already and new data are still written to it, the FIFO is will overflow and the OVRI (b2, T1/ J1-038H) will be set for indication. The interrupt on the INT pin will occur when the OVRE (b2, T1/J1-037H) is enabled. 4. When the transmission is in process and it is out of data to be
transmitted in the FIFO, the FIFO is underrun and the UDRI (b1, T1/J1038H) will be set for indication. The interrupt on the INT pin will occur when the UDRE (b1, T1/J1-037H) is enabled.
3.17 BIT-ORIENTED MESSAGE TRANSMITTER (TBOM) - T1 / J1 ONLY
The Bit Oriented Message (BOM) can only be transmitted in the ESF format in T1/J1 mode. The standard of the BOM is defined in the ANSI T1.403-1989. The Bit Oriented Message (BOM) of each framer operates independently. The BOM pattern is `111111110XXXXXX0' which occupies the DL of the F-bit in the ESF format (refer to Table - 4). The six `X's represent the code that can be programmed in the BOC[5:0] (b5~0, T1/J1-05DH). When the BOC[5:0] (b5~0, T1/J1-05DH) are written with the bits other than the `111111', they will occupy the six `X's' positions and the BOM will be transmitted. If the BOM transmission is stopped by setting all ones in the BOC[5:0] (b5~0, T1/J1-05DH), a BOM disabled pattern will be transmitted automatically. In T1 mode, the pattern is `FFFF'. In J1 mode, the pattern is `FF7E'. The disable pattern should be repeated 16 times before the HDLC bits (refer to HDLC Transmitter) are inserted in the DL bit. The transmission of the BOM takes priority over any other substitutions of the DL bit except for the Yellow alarm signal.
3.18 INBAND LOOPBACK CODE GENERATOR (IBCG) T1 / J1 ONLY
The Inband Loopback Code Generator can only transmit inband loopback code in a framed or unframed T1/J1 data stream. The Inband Loopback Code Generator of each framer operates independently. The length and the content of the inband loopback code are programmed in the CL[1:0] (b1~0, T1/J1-046H) and the IBC[7:0] (b7~0, T1/ J1-047H) respectively. The code can only be transmitted when the EN (b7, T1/J1-046H) is enabled. In framed mode, which is configured by the UF (b6, T1/J1-046H), the F-bit can be replaced by the Frame Alignment Pattern, DL and CRC-6 which are set in the Frame Generator block and the 24 channels are replaced with the inband loopback code. In unframed mode, which is configured by the UF (b6, T1/J1-046H), all 193 bits are replaced with the inband loopback code. It is recommended that the setting of the EN (b7, T1/J1-046H) and the UF (b6, T1/J1-046H) should be the same.
3.19 JITTER ATTENUATOR (RJAT/TJAT)
The Jitter Attenuator of each framer operates independently 3.19.1 E1 MODE Two Jitter Attenuators are provided independently in the receive path and the transmit path. The Jitter Attenuator integrates a FIFO and a DPLL. The smoothed clock output from the jitter attenuator is generated by adaptively dividing the 49.152MHz XCK according to the phase difference between the output smoothed clock and the input reference clock. The ratio between the frequency of the input reference clock and the frequency applied to the phase discriminator input is equal to the (N1 + 1) (the N1 is in b7~0, E1021H for receive path and in b7~0, E1-025H for transmit path). The ratio between the frequency of the output smoothed clock and the frequency applied to the phase discriminator input is equal to the (N2 + 1) (the N2
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
is in b7~0, E1-022H for receive path and in b7~0, E1-026H for transmit path). The phase fluctuations of the input reference clock are attenuated by dividing the input reference clock and output smoothed clock by the (N1 + 1) and the (N2 + 1) respectively in the DPLL so that the frequency of the output smoothed clock is equal to the average frequency of the input reference clock. The phase fluctuations with a jitter frequency above 8.8Hz are attenuated by 6dB per octave when the N1 (b7~0, E1-021H for receive path and b7~0, E1-025H for transmit path) and the N2 (b7~0, E1-022H for receive path and b7~0, E1-026H for transmit path) are set to their default value. It will change when the N1 and the N2 are changed. Generally, when the N1 and the N2 increase, the curves of the Jitter Tolerance and Jitter Transfer in the graph will left-shift and when N1 and N2 decrease, they will right-shift. The phase fluctuations (wander) with frequency below 8.8Hz are tracked by the output smoothed clock. The output smoothed clock is used to clock the data out of the FIFO. The FIFO is is 48 bits deep. If data is still written into the FIFO when the FIFO is already full, overflow will occur and the OVRI (b1, E1-020H for receive path and b1, E1-024H for transmit path) will indicate. If data is still read from the FIFO when the FIFO is already empty, under-run will occur and the UNDI (b0, E1-020H for receive path and b0, E1-024H for transmit path) will indicate. Thus, if the OVRE (b2, E1-023H for receive path and b2, E1-027H for transmit path) and the UNDE (b3, E1023H for receive path and b3, E1-027H for transmit path) are set respectively, the interrupts on the INT pin will occur. The jitter attenuation can be limited by setting the LIMIT (b0, E1-023H for receive path and b0, E1-027H for transmit path) to keep the FIFO 1UI away from being full or empty. Thus, the DPLL will track the jitter of the input reference clock by increasing or decreasing the frequency of the output smoothed clock to prevent the FIFO being empty or full. The FIFO can also selfcenter its read pointer by setting the CENT (b4, E1-023H for receive path and b4, E1-027H for transmit path). The FIFO can be set to be bypassed by the FIFOBYP (b7, E1-000H for receive path and b7, E1-002H for transmit path). However, in Transmit Clock Master mode, the TJAT should be bypassed. Jitter Characteristics Each Jitter Attenuator block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 43UIpp of input jitter at jitter frequencies above 9Hz. For jitter frequencies below 9Hz, which can be correctly called wander, the tolerance increases 20dB per decade. In most applications the each Jitter Attenuator block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The Jitter Attenuator blocks meet the low frequency jitter tolerance requirements ITU-T Recommendation G.823. The Jitter Attenuator exhibits negligible jitter gain for jitter frequencies below 9Hz, and attenuates jitter at frequencies above 9Hz by 20dB per decade. In most applications the Jitter Attenuator blocks will determine jitter attenuation for higher jitter frequencies only. Wander, below 10Hz for example, will essentially be passed unattenuated through the Jitter Attenuator. Jitter, above 10Hz for example, will be attenuated as
specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of 24X (49.152MHz) digital phase locked loop for transmit clock generation. The Jitter Attenuator meets the jitter transfer requirements of ITU-T Recommendations G.737, G.738, G.739, and G.742. Jitter Tolerance Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For the Jitter Attenuator, the input jitter tolerance is 43 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCK divided by 24 and that of the input reference clock. Refer to Figure - 63 for the Jitter Tolerance. Jitter Transfer The output jitter for jitter frequencies from 0 to 9 Hz is no more than 0.1dB greater than the input jitter. Jitter frequencies above 9 Hz are attenuated at a level of 6 dB per octave, as shown in Figure - 64. Frequency Range In the non-attenuating mode, that is, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.963 to 2.133 MHz. The guaranteed linear operating range is 2.048 MHz 1278 Hz with no jitter or XCK frequency offset.
81
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Amp.(UI)
7Hz,64UI 100 9Hz,43UI
1.667,18UI 10 4.88x10-3, 36.9UI 18UI G.823
1
18k,0.2UI 20,1.5UI 2.4k,1.5UI Frequency(Hz)
0.1 0.001
0.01
0.1
1
10
100
1000
10k
100k
Figure - 63. E1 Mode Jitter Tolerance (N1 = N2 = 2fH)
Attenuation(db) 40Hz,0.5db 0
20db/decade 9Hz,-3db
G.823
1
10
100 Frequency(Hz)
Figure - 64. E1 Mode Jitter Transfer (N1 = N2 = 2fH)
82
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.19.2 T1 / J1 MODE Two Jitter Attenuators are provided independly in the receive path and the transmit path. The Jitter Attenuator integrates a FIFO and a DPLL. The smoothed clock output from the jitter attenuator is generated by adaptively dividing the 37.056MHz XCK according to the phase difference between the output smoothed clock and the input reference clock. The ratio between the frequency of the input reference clock and the frequency applied to the phase discriminator input is equal to the (N1 + 1) (the N1 is in b7~0, T1/ J1-011H for receive path and in b7~0, T1/J1-019H for transmit path). The ratio between the frequency of the output smoothed clock and the frequency applied to the phase discriminator input is equal to the (N2 + 1) (the N2 is in b7~0, T1/J1-012H for receive path and in b7~0, T1/J1-01AH for transmit path). The phase fluctuations of the input reference clock are attenuated by dividing the input reference clock and output smoothed clock by the (N1 + 1) and the (N2 + 1) respectively in the DPLL so that the frequency of the output smoothed clock is equal to the average frequency of the input reference clock. The phase fluctuations with a jitter frequency above 6.6Hz are attenuated by 6dB per octave when the N1 (b7~0, T1/J1-011H for receive path and b7~0, T1/J1-019H for transmit path) and the N2 (b7~0, T1/J1-012H for receive path and b7~0, T1/J101AH for transmit path) are in their default value. It will change when the N1 and the N2 are changed. Generally, when the N1 and the N2 increase, the curves of the Jitter Tolerance and Jitter Transfer in the graph will left-shift and When N1 and N2 decrease, they will right-shift. The phase fluctuations (wander) with frequency below 6.6Hz are tracked by the output smoothed clock. The output smoothed clock is used to clock the data out of the FIFO. The FIFO is 48 bits deep. If data is still written into the FIFO when the FIFO is already full, overflow will occur and the OVRI (b1, T1/J1010H for receive path and b1, T1/J1-018H for transmit path) will indicate. If data is still read from the FIFO when the FIFO is already empty, underrun will occur and the UNDI (b0, T1/J1-010H for receive path and b0, T1/J1-018H for transmit path) will indicate. Thus, if the OVRE (b2, T1/J1-013H for receive path and b2, T1/J1-01BH for transmit path) and the UNDE (b3, T1/J1-013H for receive path and b3, T1/J1-01BH for transmit path) are set respectively, the interrupts on the INT pin may occur. The jitter attenuation can be limited by setting the LIMIT (b0, T1/J1013H for receive path and b0, T1/J1-01BH for transmit path) to keep the FIFO 1UI away from being full or empty,. Thus, the DPLL will track the jitter of the input reference clock by increasing or decreasing the frequency of the output smoothed clock to prevent the FIFO being empty or full. The FIFO can also self-center its read pointer by setting the CENT (b4, T1/J1-013H for receive path and b4, T1/J1-01BH for transmit path). The FIFO can be set to be bypassed by the FIFOBYP (b7, T1/J1-000H for receive path and b7, T1/J1-004H for transmit path). However, in Transmit Clock Master mode, the TJAT should be bypassed. Jitter Characteristics Each Jitter Attenuator block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 45UI of input jitter at jitter frequencies above 12HZ. For jitter frequencies below 9 Hz, which can be correctly called wander, the tolerance increases 20dB per decade. In most applications the each Jitter Attenuator block will limit jitter tolerance at lower jitter frequencies
only. For high frequency jitter, above 10kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The Jitter Attenuator blocks meet the low frequency jitter tolerance requirements AT&T TR 62411 for T1. The Jitter Attenuator exhibits negligible jitter gain for jitter frequencies below 7Hz, and attenuates jitter at frequencies above 7Hz by 20 dB per decade. In most applications the Jitter Attenuator blocks will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through DJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of 24X (37.056MHz) digital phase locked loop for transmit clock generation. The Jitter Attenuator meets the jitter transfer requirements of AT&T TR 62411. The block allows to meet the implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403. Jitter Tolerance Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For the Jitter Attenuator, the input jitter tolerance is 48 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCK divided by 24 and that of the input reference clock. Refer to Figure - 65 for the Jitter Tolerance. Jitter Transfer The output jitter for jitter frequencies from 0 to 7Hz is no more than 0.1 dB greater than the input jitter. Jitter frequencies above 7Hz are attenuated at a level of 6 dB per octave, as shown in Figure - 66. Frequency Range In the non-attenuating mode, that is, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.48 to 1.608 MHz. The guaranteed linear operating range is 1.544 MHz 963 Hz (for T1) with no jitter or XCK frequency offset.
83
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
UI(jitter) Amp.(UI) 4Hz,76UI 100 12Hz,45UI
INDUSTRIAL TEMPERATURE RANGES
138UI
4.9Hz,28UI 10
TR62411 0.31Hz,10UI 1 0.2UI 10Hz,0.3UI TR-TSY-000170 300Hz,10UI
Frequency(Hz) 0.1 0.1 1 10 100 1K 10K 100K
Figure - 65. T1/J1 Mode Jitter Tolerance (N1 = N2 = 2fH)
Attenuation(Db)
0
20Hz,0db 20db/decade
-20 7Hz,-3Db TR62411 -40
-60
-80
1
10
100
1k
10k
Frequency(Hz)
Figure - 66. T1/J1 Mode Jitter Transfer (N1 = N2 = 2fH)
84
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.20 TRANSMIT CLOCK
The Transmit Clock of each framer operates independently. 3.20.1 E1 MODE The Transmit Clock helps the Transmit Jitter Attenuator to select the source of the input reference clock for the DPLL, and selects the clock source used to drive the clock to be output on the LTCKn pin. Refer to Figure - 67 for details. 3.20.2 T1 / J1 MODE The Transmit Clock helps the Transmit Jitter Attenuator to select the source of the input reference clock for the DPLL, and selects the clock source used to drive the clock to be output on the LTCKn pin. Refer to Figure - 67 for details.
LRCKn is selected by the RCKFALL (b7, E1-001H). On the transmit line interface, the data to be transmitted on the LTDn pin are updated on the active edge of the LTCKn. The active edge of the LTCKn is selected by the LTCKRISE (b0, E1-002H). All ones can be forced to transmit on the LTDn pin when the TAISEN (b6, E1-002H) is configured. All zeros can also be forced to transmitted when the TXDIS (b0, E1-007H) is configured. 3.21.2 T1 / J1 MODE On the receive line interface, the received data on the LRDn pin are sampled on the active edge of the LRCKn. The active edge of the LRCKn is selected by the LRCKFALL (b2, T1/J1-003H). On the transmit line interface, the data to be transmitted on the LTDn pin are updated on the active edge of the LTCKn. The active edge of the LTCKn is selected by the LTCKRISE (b0, T1/J1-004H). All ones can be forced to transmitted on the LTDn pin when the TAISEN (b6, T1/J1004H) is configured. All zeros can also be forced to transmit when the TXDIS (b0, T1/J1-00AH) is configured.
3.21 LINE INTERFACE
3.21.1 E1 MODE On the receive line interface, the received data on the LRDn pin are sampled on the active edge of the LRCKn. The active edge of the
TSCCKA TSCCKB LRCK XCK/24 TSCCKA TSCCKB LRCK XCK/24 TSCCKA/8 Transmit Jitter Attenuator selected by the LTCK_SEL[2:0] (b2~0, E1-004H) / (b2~0, T1/J1-007H) Transmit Clock input reference clock DPLL output smoothed clock TSCCKA/8 LTCKn
selected by the TJATREF_SEL[2:0] (b5~3, E1-004H) / (b5~3, T1/J1-007H) FIFO data to be transmitted LTDn
Figure - 67. Transmit Clock Select
85
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
3.22 INTERRUPT SUMMARY
3.22.1 E1 MODE When the INT pin asserts low, which means at least one interrupt has occurred in the device, reading the INT[8:1] (b7~0, E1-00BH) will find in which framer the interrupt occurs. After reading the INT regiser, the interrupt source bits from the interrupting framer are read. The Interrupt Source bits (PMON [b7, E1-005H], FRMG [b6, E1-005H], FRMP [b5, E1-005H], PRGD [b4, E1-005H], ELSB [b3, E1-005H], RHDLC#1 [b2, E1-005H], RHDLC#2 [b1, E1-005H], RHDLC#3 [b0, E1-005H], TRSI [b7, E1-006H], TJAT [b5, E1-006H], RJAT [b4, E1-006H], THDLC#1 [b3, E1006H], THDLC#2 [b2, E1-006H], THDLC#3 [b1, E1-006H] and RCRB [b0, E1-006H]) will be logic 1 if there are interrupts in the corresponding block. To find the eventual interrupt sources, the interrupt Indication and Status bits in the block are polled if their Interrupt Enable bits are enabled. Then the sources are served after they are found. 3.22.2 T1 / J1 MODE When the INT pin asserts low, which means at least one interrupt has occurred in the device, reading the INT[8:1] (b7~0, T1/J1-00EH) will find that in which framer the interrupt occurs. After reading the INT regiser, the interrupt source bits from the interrupting framer are read. The Interrupt Source bits (PMON [b7, T1/J1-008H], IBCD [b6, T1/J1-008H], FRMP [b5, T1/J1-008H], PRGD [b4, T1/J1-008H], ELSB [b3, T1/J1008H], RHDLC#1 [b2, T1/J1-008H], RBOM [b1, T1/J1-008H], ALMD [b0, T1/J1-008H], RHDLC#2 [b7, T1/J1-009H], TJAT [b5, T1/J1-009H], RJAT [b4, T1/J1-009H], THDLC#1 [b3, T1/J1-009H], THDLC#2 [b2, T1/J1009H] and RCRB [b0, T1/J1-009H]) will be logic 1 if there are interrupts in the corresponding block. To find the eventual interrupt sources, the interrupt Indication and Status bits in the block are polled if their Interrupt Enable bits are enabled. Then the sources are served after they are found. However, another Interrupt Source bit PRTY (b6, T1/J1-009H) is provided to route to the pending parity error.
3.23.3 PAYLOAD LOOPBACK By programming the LOOP (b2, E1-TPLC-indirect registers-20~3FH / b2, T1/J1-TPLC-indirect registers-10~18H) (the PCCE [b0, E1-060H / b0, T1/J1-030H] in the TPLC must be logic 1), each framer can be set in the Payload Loopback mode. When Receive Clock Master modes are enabled, the Elastic Store is used to align the line received data to the frame to be transmitted. When Receive Clock Slave modes are enabled, the Elastic Store is unavailable to implement the payload loopbacks, and loop-back functionality is provided only when the Transmit System Interfaces are also in a Transmit Clock Slave mode, and the received and transmitting clocks and frame alignment are identical (RSCCK = TSCCKB, RSCFS = TSCFS). Thus, the selected timeslot/ channel in the transmit path will be overwritten by the corresponding received timeslot/channel. The remaining timeslots/channels in the transmit path are intact. Figure - 70 shows the process.
3.24 CLOCK MONITOR
The transition from low to high of the Crystal Clock (XCK), the Transmit Side System Common Clock #A (TSCCKA), the Transmit Side System Common Clock #B (TSCCKB), the Receive Side System Common Clock (RSCCK) and the Line Receive Clock (LRCK) are monitored and are reported by the XCK (b4, E1-00DH / b4, T1/J1-027H), the TSCCKB (b3, E1-00DH / b3, T1/J1-027H), the TSCCKA (b2, E1-00DH / b2, T1/J1027H), the RSCCK (b1, E1-00DH / b1, T1/J1-027H) and the LRCK (b0, E1-00DH / b0, T1/J1-027H) respectively.
3.23 LOOPBACK MODE
There are three diagnostic loopback modes: Line Loopback, Digital Loopback and Payload Loopback are provided in this device. 3.23.1 LINE LOOPBACK By programming the LINEB (b4, E1-007H / b4, T1/J1-00AH), each framer can be set in the Line Loopback mode. In this configuration, the jitter-attenuated clock and data from the Receive Jitter Attenuator are looped internally to the Line Transmit Clock and Data (LTDn and LTCKn). However, the Receive Jitter Attenuator can be bypassed if required. The received data stream is still output to the system side while the data stream input from the system side is ignored. Figure - 68 shows the process. 3.23.2 DIGITAL LOOPBACK By programming the DDLB (b2, E1-007H / b2, T1/J1-00AH), each framer can be set in the Digital Loopback mode. In this configuration, the data to be transmitted on the LTCKn and LTDn are looped internally to the Line Receive Clock and Data (LRDn and LRCKn). The data stream to be transmitted is still output to the line side while the data stream received from the line side is ignored. Figure - 69 shows the process.
86
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
One of the Eight Framers
TSCCKA TSCCKB/ MTSCCKB TSCFS/ MTSCFS MTSSIG[1:2] MTSD[1:2] TSFSn/ TSSIGn TSDn Transmit Clock Transmit System Interface
Transmit Payload Control
Frame Generator
Transmit Jitter Attenuator
LTCKn LTDn
BitInband HDLC Loopback Oriented Transmitter Message #2 #3 Code #1 Generator Transmitter
PRBS Generator /Detector
Bit-Oriented Message Receiver Alarm Detector
Inband Loopback Code Detector Line Loopback
XCK
HDLC Receiver #1 #2 #3
MRSD[1:2] MRSSIG[1:2] MRSFS[1:2] RSCCK/ MRSCCK RSCFS/ MRSCFS
RSDn RSCKn/ RSSIGn RSFSn Receive System Interface Receive Payload Control
Receive CAS/RBS Buffer Elastic Store Buffer
Frame Processor Receive Jitter Attenuator
LRCKn LRDn
Performance Monitor
Figure - 68. Line Loopback
87
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
One of the Eight Framers
TSCCKA TSCCKB/ MTSCCKB TSCFS/ MTSCFS MTSSIG[1:2] MTSD[1:2] TSFSn/ TSSIGn TSDn Transmit Clock Transmit System Interface
Transmit Payload Control
Frame Generator
Transmit Jitter Attenuator
LTCKn LTDn
BitInband HDLC Loopback Oriented Transmitter Message #2 #3 Code #1 Generator Transmitter
Digital Loopback
PRBS Generator /Detector
Bit-Oriented Message Receiver Alarm Detector
Inband Loopback Code Detector
XCK
HDLC Receiver #1 #2 #3
MRSD[1:2] MRSSIG[1:2] MRSFS[1:2] RSCCK/ MRSCCK RSCFS/ MRSCFS
RSDn RSCKn/ RSSIGn RSFSn Receive System Interface Receive Payload Control
Receive CAS/RBS Buffer Elastic Store Buffer
Frame Processor Receive Jitter Attenuator
LRCKn LRDn
Performance Monitor
Figure - 69. Digital Loopback
88
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
One of the Eight Framers
TSCCKA TSCCKB/ MTSCCKB TSCFS/ MTSCFS MTSSIG[1:2] MTSD[1:2] TSFSn/ TSSIGn TSDn Transmit Clock Transmit System Interface
Transmit Payload Control
Frame Generator
Transmit Jitter Attenuator
LTCKn LTDn
Inband Bit-Oriented HDLC Loopback Message Transmitter #2 #3 Code Transmitter #1 Generator Payload Loopback PRBS Generator /Detector Bit-Oriented Message Receiver Alarm Detector MRSD[1:2] MRSSIG[1:2] MRSFS[1:2] RSCCK/ MRSCCK RSCFS/ MRSCFS RSDn RSCKn/ RSSIGn RSFSn Receive System Interface Receive Payload Control Inband Loopback Code Detector XCK
HDLC Receiver #1 #2 #3
Receive CAS/RBS Buffer Elastic Store Buffer
Frame Processor Receive Jitter Attenuator
LRCKn LRDn
Performance Monitor
Figure - 70. Payload Loopback
89
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
4
4.1
OPERATION
E1 MODE
4.1.1 DEFAULT SETTING When the device is powered-up, all the registers contain their default values. Any of the eight framers can be reset anytime when the RESET (b0, E1-00AH / b0, T1/J1-00DH) in its framer is set. The device can also be reset anytime when the RST pin is low for at least 100ns. After the hardware reset, the IDT82V2108 will default to the following settings: Table - 39. Default Setting in Receive Path Function Block Line Interface Frame Processor HDLC Receiver #1, #2, #3 Receive System Interface
- Mode: the default operation mode of the device is T1 mode. When the E1 mode is desired, the TEMODE (b0, 400H) must be set to logic 0. - Receive Path: the default setting of each block in the receive path is illustrated in Table - 39. - Transmit Path: the default setting of each block in the transmit path is illustrated in Table - 40. 4.1.2 VARIOUS OPERATION MODES CONFIGURATION Five operation modes can be set in the receive path and four operation modes can be set in the transmit path. In each operation mode, the configurations in Table - 41 and Table - 42 are illustrated for reference.
PRGD
Default Setting Description * The LRDn inputs Non-Return to Zero (NRZ) data and are sampled on rising edge of the LRCKn. * The RJAT Clock Divisors (N1, N2) are set to `2F' . * Basic Frame per G.704 with CRC Multi-Frame enabled. * Channel Associated Signaling enabled. * RHDLCs disabled. * In Receive Clock Slave External Signaling Mode. * The data on the RSDn, RSSIGn pins are updated on rising edge of the RSCCK. * RSCFS indicates Basic Frame Alignment. * RSDn, RSSIGn, RSFSn pins are held in high-impedance state. * The PRGD is configured to monitor the extracted data patterns in Frame One.
Table - 40. Default Setting in Transmit Path Function Block PRGD Transmit System Interface Frame Generator HDLC Transmitter #1, #2, #3 Line Interface Default Setting Description * The PRGD is configured to insert test patterns to Frame One. * In Transmit Clock Slave External Signaling Mode. * The data on the TSDn and TSSIGn pins are sampled on rising edge of TSCCKB. * CRC Multi-Frame is disabled. * Channel Associated Signaling is enabled. * THDLCs are disabled. * The LTDn outputs Non-Return to Zero (NRZ) data and is updated on falling edge of LTCKn. * TJAT Clock Divisors (N1, N2) are set to `2F' * Digital jitter attenuation is enabled. The PLL is synchronized to the TSCCKB clock. The smoothed clock output from the PLL is selected as the LTCKn.
90
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 41. Various Operation Modes in Receive Path for Reference Value (from Bit7 to Bit0) Description 2 00000000 In Receive Clock Slave RSCK Reference mode. The RSCK is 8KHZ. Receive Clock 00001000 The output on the RSFSn pin is determined by the ROHM, BRXSMFP, BRCMFP and ALTIFP. Slave RSCK 010H 00100001 In Receive Clock Slave mode. The FE and DE are both 0. The receive backplane rate is 2.048Mbit/s. Reference Mode 011H 00100000 The RSCFS is used. 012H 00000001 Enable the normal operation of the RSDn pin. 001H 01000000 In Receive Clock Slave External Signaling mode. Receive Clock 00EH 00001000 The output on the RSFSn pin is determined by the ROHM, BRXSMFP, BRCMFP and ALTIFP. Slave External 010H 00100001 In Receive Clock Slave mode. The FE and DE are both 0. The receive backplane rate is 2.048Mbit/s. Signaling Mode 011H 00100000 The RSCFS is used. 012H 00000001 Enable the normal operation of the RSDn and RSSIGn pins. Receive Clock 010H 00001001 In Receive Clock Master Full E1 Mode. The FE is logic 1 and the DE is logic 0. Master Full E1 011H 00000000 The RSCFS is un-used. 012H 00000001 Enable the normal operation of the RSDn pin. Receive 010H 10001001 In Receive Clock Master Nx64K Mode. The FE is logic 1 and the DE is logic 0. Clock 011H 00000000 The RSCFS is un-used. Master 012H 00000001 Enable the normal operation of the RSDn pin. Fractional 05CH 00000011 Enable the Receive Payload Control. E1 20H-3FH (RPLC 01000000 The code in the DTRK[7:0] replaces the data output on the RSDn pin in the Mode indirect registers) corresponding channel. 001H 01001000 081H 01001000 Multiplex the data stream of these four framers to the multiplexed bus 1. 101H 01001000 Receive 181H 01001000 201H 01011000 281H 01011000 Multiplex the data stream of these four framers to the multiplexed bus 2. Multiplexed 301H 01011000 381H 01011000 010H 00111011 Mode 090H 00111011 110H 00111011 190H 00111011 In Receive Multiplexed mode. The receive backplane rate is 8.192Mbit/s. The FE 210H 00111011 is logic 1 and the DE is logic 1. 290H 00111011 310H 00111011 390H 00111011 Mode Register 1 001H 00EH
91
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 41. Various Operation Modes in Receive Path for Reference (Continued) Mode Register 1 011H 091H 111H 191H 211H 291H 311H 391H 012H 092H 112H 192H 212H 292H 312H 392H 013H 093H 113H 193H 213H 293H 313H 393H Value (from Bit7 to Bit0) 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000000 00000001 00000010 00000011 00000000 00000001 00000010 00000011 Description 2
Receive
The MRSCFS is used.
Multiplexed
Mode
Enable the normal operation of the MRSD and MRSSIG pins.
(Continued)
TSOFF[6:0] = 0. The timeslot offset is 0. TSOFF[6:0] = 1. The timeslot offset is 1. TSOFF[6:0] = 2. The timeslot offset is 2. TSOFF[6:0] = 3. The timeslot offset is 3. TSOFF[6:0] = 0. The timeslot offset is 0. TSOFF[6:0] = 1. The timeslot offset is 1. TSOFF[6:0] = 2. The timeslot offset is 2. TSOFF[6:0] = 3. The timeslot offset is 3.
Note: 1. In the `Register' column, except for the Receive Multiplexed mode, the register position of the Framer One is listed to represent the set of the registers of eight framers. The other registers position are tabulated in the `Register Map'. However, in Receive Multiplexed mode, the register position of eight framers are all listed. 2. The `Description' illustrates the fundamental function of the operation mode. The others can be configured as desired.
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INDUSTRIAL TEMPERATURE RANGES
Table - 42. Various Operation Modes in Transmit Path for Reference Mode Transmit Clock Slave External 004H Signaling Mode 027H 018H 003H 040H 004H Enable Mode 027H 018H 040H 004H 003H 083H 103H 183H 203H 283H 303H 383H 018H 098H 118H 198H 218H 298H 318H 398H 01BH 09BH 11BH 19BH 21BH 29BH 31BH 39BH Register 1 018H 003H 040H Value (from Bit7 to Bit0) Description 2 00100001 In Transmit Clock Slave mode. The FE is logic 0 and the DE is logic 0. 01000000 In Transmit Clock Slave External Signaling mode. 01110000 Channel Associated Signaling (CAS) is enabled. The CRC Multi-Frame is generated. 00001111 TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit Clock (LTCK). 00010000 The FIFO is set to self-center its read pointer. 00100001 In Transmit Clock Slave mode. The FE is logic 0 and the DE is logic 0. 00000000 In Transmit Clock Slave TSFS Enable mode. 01110000 Channel Associated Signaling (CAS) is enabled. The CRC Multi-Frame is generated. 00001111 TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit Clock (LTCK). 00010000 The FIFO is set to self-center its read pointer. 00011001 In Transmit Clock Master Full E1 mode. 01110000 Channel Associated Signaling (CAS) is enabled. The CRC Multi-Frame is generated. 00100100 XCK/24 is selected as TJAT input reference clock. XCK/24 is selected as Line Transmit Clock (LTCK). 01000000 The data stream is taken from the multiplexed bus 1. 01010000 The data stream is taken from the multiplexed bus 2. 01000000 The data stream is taken from the multiplexed bus 1. 01010000 The data stream is taken from the multiplexed bus 2. 01000000 The data stream is taken from the multiplexed bus 1. 01010000 The data stream is taken from the multiplexed bus 2. 01000000 The data stream is taken from the multiplexed bus 1. 01010000 The data stream is taken from the multiplexed bus 2. 00110011 00110011 00110011 00110011 In Transmit Multiplexed mode. The FE is logic 0 and the DE is logic 1. 00110011 00110011 00110011 00110011 00000000 TSOFF[6:0] = 0. The timeslot offset is 0. 00000000 00000001 TSOFF[6:0] = 1. The timeslot offset is 1. 00000001 00000010 TSOFF[6:0] = 2. The timeslot offset is 2. 00000010 00000011 TSOFF[6:0] = 3. The timeslot offset is 3. 00000011
Transmit Clock Slave TSFS
Transmit Clock Master Mode Transmit
Multiplexed
Mode
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Table - 42. Various Operation Modes in Transmit Path for Reference (Continued) Mode Register 1 040H 0C0H 140H 1C0H 240H 2C0H 340H 3C0H 004H 084H 104H 184H 204H 284H 304H 384H 027H 0A7H 127H 1A7H 227H 2A7H 327H 3A7H Value (from Bit7 to Bit0) 01110000 01110000 01110000 01110000 01110000 01110000 01110000 01110000 00011101 00011101 00011101 00011101 00011101 00011101 00011101 00011101 00010000 00010000 00010000 00010000 00010000 00010000 00010000 00010000 Description 2
Transmit
Channel Associated Signaling (CAS) is enabled. The CRC Multi-Frame is generated.
Multiplexed
Mode
TSCCKA is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit Clock (LTCK).
(Continued)
The FIFO is set to self-center its read pointer.
Note: 1. In the `Register' column, except for the Transmit Multiplexed mode, the register position of the Framer One is listed to represent the set of the registers of eight framers. The other registers position are tabulated in the `Register Map'. However, in Transmit Multiplexed mode, the register position of eight framers are all listed. 2. The `Description' illustrates the fundamental function of the operation mode. The others can be configured as desired.
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INDUSTRIAL TEMPERATURE RANGES
4.1.3 OPERATION EXAMPLE In this chapter, some common operation examples are given for reference. 4.1.3.1 Using The HDLC Receiver Before using the HDLC Receiver, the TXCISEL (b3, E1-00AH) must be set to 0 to enable the HDLC data link position for receive path. Since three HDLC Receive data links are integrated in one framer, one of the three HDLC Receive data links must be selected in the RHDLCSEL[1:0] (b7~6, E1-00AH). Then the HDLC data link can be configured to extract from even and/or odd frames, from any timeslot, and from any bit. The following examples show how to select the HDLC Receiver data link positions: a. to extract the HDLC data link from all bits of TS16 in HDLC Receive #1: - set the TXCISEL (b3, E1-00AH) to 0; - set the RHDLCSEL[1:0] (b7~6, E1-00AH) to 00; - set the DL1_EVEN (b7, E1-028H) to 0; - set the DL1_ODD (b6, E1-028H) to 0; - set the TS16_EN (b5, E1-028H) to 1. b. to extract the HDLC data link from the Sa8 National bit in HDLC Receive #1: - set the TXCISEL (b3, E1-00AH) to 0; - set the RHDLCSEL[1:0] (b7~6, E1-00AH) to 00; - set the DL1_EVEN (b7, E1-028H) to 0; - set the DL1_ODD (b6, E1-028H) to 1; - set the TS16_EN (b5, E1-028H) to 0; - set the DL1_TS[4:0] (b4~0, E1-028H) to 00000 - set the DL1_BIT[7:0] (b7~0, E1-029H) to 00000001. c. to extract the HDLC data link from all bits of TS20 of all frames in HDLC Receive #2: - set the TXCISEL (b3, E1-00AH) to 0; - set the RHDLCSEL[1:0] (b7~6, E1-00AH) to 01; - set the DL2_EVEN (b7, E1-02AH) to 1; - set the DL2_ODD (b6, E1-02AH) to 1; - set the DL2_TS [4:0] (b4~0, E1-02AH) to 10100; - set the DL2_BIT [7:0] (b7~0, E1-02BH) to 11111111. After setting the HDLC data link position properly, the selected HDLC Receiver should be enabled by setting the EN (b0, E1-048H)to logic 1. If needed, set the MEN (b3, E1-048H) and the MM (b2, E1048H) to determine which Address Matching Mode to be selected (refer to Register Description for details). After setting these 3 bits, the RHDLC Primary Address Match register and the RHDLC Secondary Address Match register should be set to proper values. If the INTC[6:0] (b6~0, E1-049H) are set, whenever the number of bytes in the RHDLC FIFO exceeds the value set in the INTC[6:0] (b6~0, E1-049H), the INTR (b0, E1-04AH) will be set to logic 1. This interrupt will persist until the RHDLC FIFO becomes empty. Setting the INTE (b7, E1-049H) to logic 1 allows the internal interrupt status to be propagated to the INT output pin. After setting these registers properly, the HDLC data can be received in a polled or interrupt driven mode. - Interrupt Driven Mode When the INTE (b7, E1-049H) is set to logic 1, if the INT pin is asserted, the source of the interrupt should be first identified by reading
the Interrupt ID register and Interrupt Source registers. If the source of the interrupt is HDLC Receive, the Interrupt Service procedure will be carried out as shown in Figure - 71. - Polling Mode In polling mode, the operation procedure is the same as Figure - 71, except that the entry of the service is from a local timer rather than an interrupt. To summarize the procedure of using HDLC Receive, a complete example is shown in Table - 43. Table - 43. Example for Using HDLC Receiver Description RHDLC #2 is selected. The HDLC Receive is accessable to the CPU interface. 02AH C4H The TS4 of even frames and odd frames are selected. 02BH FFH All the 8 bits are selected. 048H 0DH The function of the RHDLC #2 is enabled. Set the address match mode. 049H 8FH Set the INTE to 1. When the number of bytes in the RHDLC FIFO exceeds 15, an interrupt is generated. 04CH 13H The primary address is set to 13H. 04DH FFH The secondary address is set to FFH. Then read the data status in register 04AH. Until a complete packet is received, read the data from register 04BH. Register Value 00AH 50H
4.1.3.2 Using The HDLC Transmitter Before using the HDLC Transmit, the TXCISEL (b3, E1-00AH) must be set to 1 to enable the HDLC data link position for transmit path. Since three HDLC Transmit data links are integrated in one framer, one of the three HDLC Transmit data links must be selected in the THDLCSEL[1:0] (b5~4, E1-00AH). Then the HDLC data link can be configured to insert to even and/or odd frames, to any timeslot, and to any bit. The following examples show how to select the HDLC Transmit data link positions: a. to insert the HDLC data link to all bits of TS16 in HDLC Transmit #1: - set the TXCISEL (b3, E1-00AH) to 1; - set the THDLCSEL [1:0] (b5~4, E1-00AH) to 00; - set the DL1_EVEN (b7, E1-028H) to 0; - set the DL1_ODD (b6, E1-028H) to 0; - set the TS16_EN (b5, E1-028H) to 1. b. to insert the HDLC data link to the Sa4-Sa8 National bits in HDLC Transmit #1: - set the TXCISEL (b3, E1-00AH) to 1; - set the THDLCSEL [1:0] (b5~4, E1-00AH) to 00; - set the DL1_EVEN (b7, E1-028H) to 0; - set the DL1_ODD (b6, E1-028H) to 1; - set the TS16_EN (b5, E1-028H) to 0;
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INDUSTRIAL TEMPERATURE RANGES
INT asserts RHDLC interrupt N Other block interrupt service
Y Read RHDLC STATUS OVR=1 N COLS=1 N PKIN=1 Y PACKET COUNT * increment N Read RHDLC data Read RHDLC status OVR=1 N COLS=1 N PKIN=1 Y 000 N PBS[2:0]=? 1XX store the packet data 001 Discard this data byte, Set LINK ACTIVE * Flag 010 Store this byte, decrement the PACKET COUNT *, check for CRC or non-integer number of bytes errors before deciding whether to keep the packet or not. PACKET COUNT * increment Y Set EMPTY FIFO * flag Y Discard the last packet Y Set EMPTY FIFO flag Y Discard the last packet
Discard this data byte, Clear LINK ACTIVE * Flag
N
FE=1 Y End of Interrupt Service
Note: * The PACKET COUNT, EMPTY FIFO and LINK ACTIVE are local software variable.
Figure - 71. Interrupt Service in E1 Mode HDLC Receiver
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INDUSTRIAL TEMPERATURE RANGES
- set the DL1_TS[4:0] (b4~0, E1-028H) to 00000 - set the DL1_BIT[7:0] (b7~0, E1-029H) to 00011111. c. to insert the HDLC data link to all bits of TS20 of all frames in HDLC Transmit #3: - set the TXCISEL (b3, E1-00AH) to 1; - set the THDLCSEL [1:0] (b5~4, E1-00AH) to 10; - set the DL3_EVEN (b7, E1-02CH) to 1; - set the DL3_ODD (b6, E1-02CH) to 1; - set the DL3_TS [4:0] (b4~0, E1-02CH) to 10100; - set the DL3_BIT [7:0] (b7~0, E1-02DH) to 11111111. After setting the HDLC data link position properly, the selected HDLC Transmit should be enabled by setting the EN (b0, E1-050H) to logic 1. The FIFOCLR (b6, E1-050H) should be set and then cleared to initialize the THDLC FIFO. Set the CRC (b1, E1-050H) to logic 1 if the Frame Check Sequences (FCS) generation is desired. Set the FULLE (b3, E1-053H), OVRE (b2, E1-053H), UDRE (b1, E1-053H) and LFILLE (b0, E1-053H) to logic 1 if interrupt driven mode is used. Set THDLC Upper Transmit Threshold and THDLC Lower Transmit Threshold registers to the desired values. If a complete packet has been written into THDLC FIFO, the EOM (b3, E1-050H) should be set. After setting these registers properly, the HDLC data can be transmitted in a polled or interrupt driven mode. - Interrupt Driven Mode Writing HDLC data to THDLC FIFO , the THDLC will transmit the HDLC data if the end of a packet was written or if the THDLC FIFO fill level reaches the Upper Transmit Threshold. The writing procedure is shown in Figure - 72. When the FULLE (b3, E1-053H), OVRE (b2, E1-053H), UDRE (b1, E1-053H) and LFILLE (b0, E1-053H) are set to logic 1, if the INT pin is asserted, the source of the interrupt should be identified firstly by reading the Interrupt ID register and Interrupt Source registers. If the source of the interrupt is HDLC Transmit, the Interrupt Service procedure will be carried out as shown in Figure - 73. - Polling Mode In packet transmission polling mode, the FULLE (b3, E1-053H), OVRE (b2, E1-053H), UDRE (b1, E1-053H) and LFILLE (b0, E1-053H) should be set to logic 0. The THDLC Lower Transmit Threshold should be set to such a value that sufficient warning of an underrun is given. The procedure shown in Figure - 74 should be followed. To summarize the procedure of using HDLC Transmit, a complete example is shown in Table - 44.
THDLC Initial
Data is available
N
Y Write data into THDLC FIFO
End of packet Y Set EOM
N
Figure - 72. Writing Data to E1 Mode THDLC FIFO
Table - 44. Example for Using HDLC Transmitter Register Value 00AH 58H 02AH 02BH 050H 050H 053H 055H 055H 055H 055H 055H 055H 055H 055H 050H C4H FFH C3H 83H 0FH 12H 34H 56H 78H 9AH BCH DEH FFH 8BH Description THDLC #2 is selected. The HDLC Transmit is accessable to the CPU interface. The TS4 of even frames and odd frames are selected. All the 8 bits are selected. The function of the THDLC #2 is enabled. The FCS is enables and the THDLC FIFO is reset. Enable the THDLC Interrupt Enable bits.
Write data into THDLC FIFO.
End of packet and set the EOM to 1.
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INDUSTRIAL TEMPERATURE RANGES
INT Asserts N Other Blocks Interrupt Service
THDLC Interrupt Y Y UNDRI=1 N Y OVRI=1 N FULLI=1 Set the RLP Flag 1 N LFILLI=1 Y BLFILL=1 Y End of packet Y Set EOM End of Interrupt Service N N N Y
FULL=1
Y N
Start a timer 2
Note: 1. RLP-Retransmit the last packet, a local software variable. 2. A local timer to wait for a certain time until the Full = 0 or the BLFILL = 1.
Figure - 73. Interrupt Service in E1 Mode HDLC Transmitter
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INDUSTRIAL TEMPERATURE RANGES
THDLC initial
Data is available Y Read THDLC interrupt status FULL=1 N Write the data into the THDLC FIFO Y More Data to be tarnsmitted N Set EOM
N
Y
Wait, until FULL=0 or BBLFILL=1
Figure - 74. Polling Mode in E1 Mode HDLC Transmitter
4.1.3.3 Using The PRBS Generator / Detector The IDT82V2108 provides one PRBS generator/detector block to generate and detect an enormous variety of pseudo-random and repetitive patterns to diagnose E1 data stream of all eight framers. The common test patterns are shown in tabular form in Table - 45. The PRBS generator/detector block can be used to test E1 line transmit-receive integrity and system backplane integrity. - Example For Testing E1 Line Transmit-Receive Integrity To monitor the errors in Framer 2 without taking the entire E1 span off line, the following procedure should be done: - Use the PRGD block to test Framer 2; - Configure the PRGD register; - Chose a desired set of timeslots (for example TS2, TS4, TS5) for insertion/extraction of PRGD test data; - Set the far end of the line to loop back at least the selected timeslots; - Monitor the E1 line transmit-receive integrity. To realize the above function, the configuration in Table - 46 to Table 48 should be set. Table - 46 is the configuration for PRGD and loopback. Table - 47 shows the process to initialize the TPLC. Table - 48 shows the process to initialize the RPLC.
After the above settings, read the PRGD Interrupt Enable/Status (071H) register twice. If the SYNCV (b4, E1-071H) is logic 1 and the BEI (b2, E1-071H) is logic 0, the pattern detector is in synchronization state. Then insert errors into this link. Here suppose to insert 3 errors, then the configuration is shown in Table - 49. - Example For Testing E1 System Backplane Integrity To test the E1 system backplane integrity, the RXPATGEN (b2, E100CH) should be set to logic 1 and the other registers are set as above. Then the PRGD can be used to test the system backplane integrity.
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Table - 45. Test Pattern Pseudo-Random Pattern Generation (the PS [b4, E1-070H] is logic 0) Pattern Type TR 1 LR 2 IR#1 3 IR#2 4 IR#3 5 IR#4 6 3 -1 2 00 02 FF FF FF FF 2 4 -1 00 03 FF FF FF FF 2 5 -1 01 04 FF FF FF FF 2 6 -1 04 05 FF FF FF FF 7 -1 (Fractional T1 LB Activate) 2 00 06 FF FF FF FF 2 7 -1 (Fractional T1 LB Activate) 03 06 FF FF FF FF 2 7 -1 03 06 FF FF FF FF 9 -1 (O.153) 2 04 08 FF FF FF FF 2 10 -1 02 09 FF FF FF FF 2 11 -1 (O.152,O.153) 08 0A FF FF FF FF 15 -1 (O.151) 2 0D 0E FF FF FF FF 2 17 -1 02 10 FF FF FF FF 2 18 -1 06 11 FF FF FF FF 02 13 FF FF FF FF 2 20 -1 (O.153) 2 21 -1 01 14 FF FF FF FF 22 -1 2 00 15 FF FF FF FF 2 23 -1 (O.151) 11 16 FF FF FF FF 2 25 -1 02 18 FF FF FF FF 28 -1 2 02 1B FF FF FF FF 2 29 -1 01 1C FF FF FF FF 31 -1 2 02 1E FF FF FF FF Repetitive Pattern Generation (the PS [b4, E1-070H] is logic 1) TR 1 LR 2 IR#1 3 IR#2 4 IR#3 5 IR#4 6 00 00 FF FF FF FF 00 00 FE FF FF FF 00 01 FE FF FF FF 00 03 FC FF FF FF 00 17 22 00 20 FF 00 0F 01 00 FF FF 00 07 01 FF FF FF 00 03 F1 FF FF FF 00 04 F0 FF FF 0F 00 02 FC FF FF FF
TINV 7 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0
RINV 7 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0
Pattern Type All ones All zeros Alternatingones/zeros Double alternatingones/zeros 3 in 24 1 in 16 1 in 8 1 in 4 DS1 Inbandloopback activate DS1 InbandLoopback deactivate
TINV 7 0 0 0 0 0 0 0 0 0 0
RINV 7 0 0 0 0 0 0 0 0 0 0
Note: 1. TR - Tap Register 2. LR - Shift Register Length Register 3. IR#1 - PRGD Pattern Insertion #1 Register 4. IR#2 - PRGD Pattern Insertion #2 Register 5. IR#3 - PRGD Pattern Insertion #3 Register 6. IR#4 - PRGD Pattern Insertion #4 Register 7. TINV, RINV - contained in the PRGD Control register
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INDUSTRIAL TEMPERATURE RANGES
Table - 46. The Setting of PRGD Register Value 00CH 20H Description Select Framer 2 to be tested by the PRGD block. The PRGD pattern is inserted in the TPLC and detected in the RPLC. Set Pattern Detector registers as error counter register. Enable automatic resynchronization. Set the pattern length. Set the feedback tap position. Set the Pattern Insertion registers. Load the data in the Pattern Insertion registers to generate the pattern. Set diagnostic digital loopback mode. Enable the TPLC indirect registers to be accessable. Enable the RPLC indirect registers to be accessable.
Table - 47. Initializtion of TPLC (Continued) Register 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H
101
070H 072H 073H 078H 07BH 087H 0E0H 0DCH
82H 18H 02H FFH FFH 04H 01H 01H
Table - 47. Initializtion of TPLC Register 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H Value 00H 20H 00H 21H 00H 22H 00H 23H 00H 24H 00H 25H 00H 26H 00H 27H 00H 28H 00H 29H 00H 2AH 00H 2BH 00H 2CH 00H 2DH
Value 00H 2EH 00H 2FH 00H 30H 00H 31H 00H 32H 00H 33H 00H 34H 00H 35H 00H 36H 00H 37H 00H 38H 00H 39H 00H 3AH 00H 3BH 00H 3CH 00H 3DH 00H 3EH 00H 3FH 00H 60H 00H 61H 00H 62H 00H 63H 00H 64H 00H 65H
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 47. Initializtion of TPLC (Continued) Register 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H Value 00H 66H 00H 67H 00H 68H 00H 69H 00H 6AH 00H 6BH 00H 6CH 00H 6DH 00H 6EH 00H 6FH 00H 70H 00H 71H 00H 72H 00H 73H 00H 74H 00H 75H 00H 76H 00H 77H 00H 78H 00H 79H 00H 7AH 00H 7BH 00H 7CH 00H 7DH
Table - 47. Initializtion of TPLC (Continued) Register 0E3H 0E2H 0E3H 0E2H Value 00H 7EH 00H 7FH
Then set the TEST in TPLC Payload Control register for TS2, TS4 and TS5. The process is: Register Value Description 0E3H 08H Set the TEST in TPLC Payload Control register 0E2H 22H for TS2. 0E3H 08H Set the TEST in TPLC Payload Control register 0E2H 24H for TS4. 0E3H 08H Set the TEST in TPLC Payload Control register 0E2H 25H forTS5.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 48. Initializtion of RPLC Register 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH Value 00H 20H 00H 21H 00H 22H 00H 23H 00H 24H 00H 25H 00H 26H 00H 27H 00H 28H 00H 29H 00H 2AH 00H 2BH 00H 2CH 00H 2DH 00H 2EH 00H 2FH 00H 30H 00H 31H 00H 32H 00H 33H 00H 34H 00H 35H 00H 36H 00H 37H
Table - 48. Initializtion of RPLC (Continued) Register 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH Value 00H 38H 00H 39H 00H 3AH 00H 3BH 00H 3CH 00H 3DH 00H 3EH 00H 3FH
Then set the TEST in RPLC Payload Control register for TS2, TS4 and TS5. The process is: Register Value Description 0DFH 80H Set the TEST in RPLC Payload Control 0DEH 22H register for TS2. 0DFH 80H Set the TEST in RPLC Payload Control 0DEH 24H register for TS4 0DFH 80H Set the TEST in RPLC Payload Control 0DEH 25H register for TS5
Table - 49. Error Insertion Register 074H 074H 074H 074H 074H 074H Value 08H 00H 08H 00H 08H 00H
Then write 00H into the 07CH register to update the error counter registers. Then read the registers from 07CH to 07FH to check the error numbers.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
4.1.3.4 Using Payload Control and Receive CAS/RBS Buffer Before using the Receive/Transmit Payload Control and Receive CAS/RBS Buffer, the indirect registers of these blocks must be initialized to eliminate erroneous control data. The PCCE (b0, E1-05CH & b0, E1060H & b0, E1-064H) of these blocks must be set to logic 1 to enable these blocks. Then the BUSY (b7, E1-05DH & b7, E1-061H & b7, E1-065H) must be checked before a new access request to the RPLC, TPLC and RCRB indirect registers. When the BUSY is logic 0, the new reading and writing access operations can be performed. Figure - 75 shows the writing sequence of the RPLC, TPLC and RCRB indirect registers. Figure - 76 shows the reading sequence of the RPLC, TPLC and RCRB indirect registers. 4.1.3.5 Using TJAT / Timing Option In different operation modes, the Timing Options and Clock Divisor Control registers can be set as the follows: - Transmit Clock Slave Mode (System Backplane Rate: 2.048M bit/s) The TSCCKA or TSCCKB is selected as the TJAT DPLL input reference clock. The TSCCKA and TSCCKB are both equal to 2.048M. The N1 (b7~0, E1-025H) and N2 (b7~0, E1-026H) are set to their default value (2FH). The smoothed clock output from the TJAT is selected as the LTCK. - Transmit Clock Slave Mode (System Backplane Rate: 4.096M bit/s) The TSCCKA is selected as the TJAT DPLL input reference clock. The TSCCKA is equal to 2.048M. The N1 (b7~0, E1-025H) and N2 (b7~0, E1-026H) are set to their default value (2FH). The smoothed clock output from the TJAT is selected as the LTCK. - Transmit Clock Master Mode The XCK/24 is selected as the TJAT DPLL input reference clock. The XCK/24 is selected as the LTCK. - Transmit Multiplexed Mode (System Backplane Rate: 8.192M bit/s) The TSCCKA is selected as the TJAT DPLL input reference clock. The TSCCKA is equal to 2.048M. The N1 (b7~0, E1-025H) and N2 (b7~0, E1-026H) are set to their default value (2FH). The smoothed clock output from the TJAT is selected as the LTCK. - Transmit Multiplexed Mode (System Backplane Rate: 16.384M bit/s) The TSCCKA or TSCCKA/8 is selected as the TJAT DPLL input reference clock. The TSCCKA is equal to 2.048M or 16.384M. The N1 (b7~0, E1-025H) and N2 (b7~0, E1-026H) are set to their default value (2FH). The smoothed clock output from the TJAT is selected as the LTCK.
Set PCCE=1
BUSY=0 Y
N
Data are set in the Channel Indirect Data Buffer Register RWB=0 and address is specified in the Channel Indirect Address/ Control Register.
Y
More data to be written N End
Figure - 75. Writing Sequence of Indirect Register in E1 Mode
Set PCCE=1 N
BUSY=0
Y RWB=1 and address is specified in the Channel Indirect Address/ Control Register. N
BUSY=0 Y
Read Channel Indirect Data Buffer Register Y
More data to be read N End
Figure - 76. Reading Sequence of Indirect Register in E1 Mode
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
4.2
T1/J1 MODE
4.2.1 DEFAULT SETTING When the device is power up, all the registers are in their default values. Any of the eight framers can be reset anytime when the RESET (b0, E1-00AH / b0, T1/J1-00DH) in its framer is set. The device can also be reset anytime when the RST pin is low for at least 100ns. After the hardware reset, the IDT82V2108 will default to the following settings: - Mode: the default operation mode of the device is T1 mode. - Receive Path: the default setting of each block in the receive path is illustrated in the Table - 50. - Transmit Path: the default setting of each block in the transmit path is illustrated in the Table - 51. 4.2.2 OPERATION IN J1 MODE IDT82V2108 can also be operated in J1 mode when the TEMODE (b0, 400H) is set to logic 1. Except for the setting of the JYEL in bit 3 of FRMP Configuration registers (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H), the J1_YEL in bit 5 of ALMD Configuration registers (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH), the J1_YEL Table - 50. Default Setting in Receive Path Function Block Line Interface Frame Processor HDLC Receiver #1, #2 Receive System Interface
in bit 5 and the J1_CRC in bit 6 of FRMG Configuration registers (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H), the setting of the other registers are the same as the setting in T1 mode. The follows illustrate the setting in J1 mode difference from the setting in the T1 mode. In receive path, set the JYEL in bit 3 of FRMP Configuration registers (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H) to logic 1, the Frame Processor will operate in J1 mode. Set the J1_YEL in bit 5 of ALMD Configuration registers (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH) to logic 1, the Alarm Detector will operate in J1 mode. In transmit path, set the J1_CRC in bit 6 of FRMG Configuration registers (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H) to logic 1, the Frame Generator will generate J1 frame. Set the J1_YEL in bit 5 of FRMG Configuration registers (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H) to logic 1, the IDT82V2108 will transmit the Yellow alarm in J1 format if Yellow alarm transmission is enabled. 4.2.3 VARIOUS OPERATION MODES CONFIGURATION Five operation modes can be set in the receive path and four operation modes can be set in the transmit path. In each operation modes, the configurations in Table - 52 and Table - 53 are illustrated for reference.
Receive Payload Control PRGD
Default Setting Description * The LRDn inputs Non-Return to Zero (NRZ) data and is sampled on rising edge of the LRCKn. * The RJAT Clock Divisors (N1, N2) are set to `2F'. * Super Frame (SF) format is enabled. * RHDLCs are disabled. * In Recieve Clock Slave External Signaling Mode. * The data on the RSDn, RSSIGn pins are updated on falling edge of the RSCCK. * RSCFS indicates each F-bit. * The data on the RSDn, RSSIGn, RSFSn pins are held in high-impedance state. * The RPLC is disabled. * The PRGD is configured to monitor the extracted data patterns in Frame One.
Table - 51. Default Setting in Transmit Path Function Block PRGD Transmit System Interface Default Setting Description * The PRGD is configured to insert test patterns to Frame One. * In Transmit Clock Slave External Signaling Mode. * The data on the TSDn and TSSIGn pins are sampled on rising edge of TSCCKB. Transmit Payload Control * The TPLC is disabled. Frame Generator * Super Frame (SF) format is enabled. HDLC Transmitter #1, #2 * THDLCs are disabled. Bit-Oriented Message Transmitter * The BOMT is disabled. Inband Loop-back Code Generator * The Inband Loop-back Code Generator is disabled. Line Interface * The LTDn outputs Non-Return to Zero (NRZ) data and is updated on falling edge of LTCKn. * TJAT Clock Divisors (N1, N2) are set to `2F' * Digital jitter attenuation is enabled. The PLL is synchronized to the TSCCKB clock. The smoothed clock output from the PLL is selected as the LTCKn.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 52. Various Operation Modes in Receive Path for Reference Value (from Bit7 to Bit0) Description 2 10000000 In Receive Clock Slave RSCK Reference mode. Receive Clock 00010011 Enable the normal operation of the RSDn pin. The data on the RSDn are updated on the rising edge of the RSCCK. The data on the RSCFS are Slave RSCK sampled on the falling edge of the RSCCK. 020H 00110000 The Frame Processor is set in ESF format. The CRC-6 calculation is Reference Mode performed when mimic framing pattern is present. 02CH 00010000 The Alarm Detector is set in ESF format. 040H 00000100 The Receive CAS/RBS Buffer is set in ESF format. 001H 11000000 In Receive Clock Slave External Signaling mode. The backplane rate is Receive 1.544Mbit/s. 003H 00010011 Enable the normal operation of the RSDn and RSSIGn pins. The data on the (1.544M RSDn and RSSIGn are updated on the rising edge of the RSCCK. The data Clock on the RSCFS are sampled on the falling edge of the RSCCK. bit/s) 020H 00110000 The Frame Processor is set in ESF format. The CRC-6 calculation is performed when mimic framing pattern is present. Slave 02CH 00010000 The Alarm Detector is set in ESF format. 040H 00000100 The Receive CAS/RBS Buffer is set in ESF format. 001H 11010000 In Receive Clock Slave External Signaling mode. The backplane rate is External 2.048Mbit/s. 003H 00010011 Enable the normal operation of the RSDn and RSSIGn pins. The data on the (2.048M RSDn and RSSIGn are updated on the rising edge of the RSCCK. The data Signaling on the RSCFS are sampled on the falling edge of the RSCCK. bit/s) 020H 00110000 The Frame Processor is set in ESF format. The CRC-6 calculation is performed when mimic framing pattern is present. Mode 02CH 00010000 The Alarm Detector is set in ESF format. 040H 00000100 The Receive CAS/RBS Buffer is set in ESF format. 001H 01000000 In Receive Clock Master Full T1/J1 mode. Receive Clock 003H 00010000 Enable the normal operation of the RSDn pin. The data on the RSDn and Master Full RSFSn are updated on the rising edge of the RSCK. T1/J1 Mode 020H 00000000 The Frame Processor is set in SF format. 02CH 00000000 The Alarm Detector is set in SF format. 040H 00000000 The Receive CAS/RBS Buffer is set in SF format. 001H 00000000 In Receive Clock Master Nx64k mode. Receive Clock 003H 00010000 Enable the normal operation of the RSDn pin. The data on the RSDn and RSFSn are updated on the rising edge of the RSCK. 020H 00110000 The Frame Processor is set in ESF format. The CRC-6 calculation is Master Fractional performed when mimic framing pattern is present. 02CH 00010000 The Alarm Detector is set in ESF format. 040H 00000100 The Receive CAS/RBS Buffer is set in ESF format. T1/J1 Mode 050H 00000001 Enable the Receive Payload Control. 01H-18H (RPLC 01000000 The code in the DTRK[7:0] replaces the data output on the RSDn pin in the Indirect Registers) corresponding channel. Mode Register 1 001H 003H
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 52. Various Operation Modes in Receive Path for Reference (Continued) Register 1 001H 081H 101H 181H 201H 281H 301H 381H 003H 083H 103H Receive 183H 203H 283H 303H 383H 077H 0F7H 177H 1F7H 277H 2F7H 377H Multiplexed 3F7H 020H 0A0H 120H 1A0H 220H 2A0H 320H 3A0H 02CH 0ACH 12CH Mode 1ACH 22CH 2ACH 32CH 3ACH 040H 0C0H 140H 1C0H 240H 2C0H 340H 3C0H Mode Value (from Bit7 to Bit0) 11001000 11001000 11001000 11001000 11001000 11001000 11001000 11001000 01010011 01010011 01010011 01010011 11010011 11010011 11010011 11010011 00000000 00000001 00000010 00000011 00000000 00000001 00000010 00000011 00110000 00110000 00110000 00110000 00110000 00110000 00110000 00110000 00010000 00010000 00010000 00010000 00010000 00010000 00010000 00010000 00000100 00000100 00000100 00000100 00000100 00000100 00000100 00000100 Description 2
In Receive Multiplexed mode. The receive backplane rate is 8.192Mbit/s.
Multiplex the data stream of these four framers to the multiplexed bus 1. Enable the normal operation of the MRSD and MRSSIG pins. The data on the MRSD and MRSSIG are updated on the rising edge of the MRSCCK. The data on the MRSCFS are sampled on the falling edge of the MRSCCK. Multiplex the data stream of these four framers to the multiplexed bus 2. Enable the normal operation of the MRSD and MRSSIG pins. The data on the MRSD and MRSSIG are updated on the rising edge of the MRSCCK. The data on the MRSCFS are sampled on the falling edge of the MRSCCK. TSOFF[6:0] = 0. The timeslot offset is 0. TSOFF[6:0] = 1. The timeslot offset is 1. TSOFF[6:0] = 2. The timeslot offset is 2. TSOFF[6:0] = 3. The timeslot offset is 3. TSOFF[6:0] = 0. The timeslot offset is 0. TSOFF[6:0] = 1. The timeslot offset is 1. TSOFF[6:0] = 2. The timeslot offset is 2. TSOFF[6:0] = 3. The timeslot offset is 3.
The Frame Processor is set in ESF format. The CRC-6 calculation is performed when mimic framing pattern is present.
The Alarm Detector is set in ESF format.
The Receive CAS/RBS Buffer is set in ESF format.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 53. Various Operation Modes in Transmit Path for Reference Mode Transmit Clock Slave TSFS Enable Mode 01BH 004H Transmit 005H Clock (1.544M bit/s) 044H 007H 01BH 004H 005H 044H 007H 019H 01AH 01BH 004H 005H 044H 007H 004H 084H 104H 184H 204H 284H 304H 384H 005H 085H 105H 185H 205H 285H 305H 385H 005H 044H 007H Register 1 004H Value (from Bit7 to Bit0) Description 2 00001000 The data on the TSDn and TSCFS pins are sampled on the falling edge of the TSCCKB. The data on the TSFSn pin are updated on the falling edge of the TSCCKB. 10000000 In Transmit Clock Slave TSFS Enabled mode. The backplane rate is 1.544Mbit/s. 00010000 The Frame Generator is set in ESF format. 00001101 TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit Clock (LTCK). 00010000 The FIFO is set to self-center its read pointer. 00001000 The data on the TSDn, TSSIGn and TSCFS pins are sampled on the falling edge of the TSCCKB. 11000000 In Transmit Clock Slave External Signaling mode. The backplane rate is 1.544Mbit/s. 00010000 The Frame Generator is set in ESF format. 00001101 TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit Clock (LTCK). 00010000 The FIFO is set to self-center its read pointer. 00001000 The data on the TSDn, TSSIGn and TSCFS pins are sampled on the falling edge of the TSCCKB. 11000100 In Transmit Clock Slave External Signaling mode. The backplane rate is 2.048Mbit/s. 00010000 The Frame Generator is set in ESF format. 00001101 TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit Clock (LTCK). 11111111 Set the Reference Clock Divisor(N1) to 255. 11000000 Set the Output Clock Divisor(N2) to 192. 00010000 The FIFO is set to self-center its read pointer. 00000110 The data on the TSFSn pin are updated on the rising edge of the LTCK. The data on the TSDn pin are sampled on the falling edge of the LTCK. 01000000 In Transmit Clock Master Full T1/J1 mode. The backplane rate is 1.544Mbit/s. 00000000 The Frame Generator is set in SF format. 00100100 XCK/24 is selected as TJAT input reference clock and Line Transmit Clock (LTCK). 00001000 00001000 00001000 00001000 The data on the TSDn, TSSIGn and TSCFS pins are sampled on the falling edge 00001000 of TSCCKB. 00001000 00001000 00001000 11001100 11001100 11001100 11001100 In Transmit Multiplexed mode. The backplane rate is 8.192Mbit/s. 11001100 11001100 11001100 11001100
Slave
External (2.048M Signaling bit/s)
Mode
Transmit Clock Master Mode
Transmit
Multiplexed
Mode
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 53. Various Operation Modes in Transmit Path for Reference (Continued) Mode Register 1 014H 094H 114H 194H 214H 294H 314H 394H 015H 095H 115H 195H 215H 295H 315H 395H 044H 0C4H 144H 1C4H 244H 2C4H 344H 3C4H 007H 087H 107H 187H 207H 287H 307H 387H 019H 099H 119H 199H 219H 299H 319H 399H 01AH 09AH 11AH 19AH 21AH 29AH 31AH 39AH Value (from Bit7 to Bit0) 00000000 00000000 00000001 00000001 00000010 00000010 00000011 00000011 00000000 01000000 00000000 01000000 00000000 01000000 00000000 01000000 00010000 00010000 00010000 00010000 00010000 00010000 00010000 00010000 00011101 00011101 00011101 00011101 00011101 00011101 00011101 00011101 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11000000 11000000 11000000 11000000 11000000 11000000 11000000 11000000 Description 2 TSOFF[6:0] = 0. The timeslot offset is 0. TSOFF[6:0] = 1. The timeslot offset is 1. TSOFF[6:0] = 2. The timeslot offset is 2. TSOFF[6:0] = 3. The timeslot offset is 3. The data stream is taken from the multiplexed bus 1. The data stream is taken from the multiplexed bus 2. The data stream is taken from the multiplexed bus 1. The data stream is taken from the multiplexed bus 2. The data stream is taken from the multiplexed bus 1. The data stream is taken from the multiplexed bus 2. The data stream is taken from the multiplexed bus 1. The data stream is taken from the multiplexed bus 2.
Transmit
Multiplexed
The Frame Generator is set in ESF format.
Mode
TSCCKA is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit Clock (LTCK).
(Continued)
Set the Reference Clock Divisor(N1) to 255.
Set the Output Clock Divisor(N2) to 192.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 53. Various Operation Modes in Transmit Path for Reference (Continued) Mode Transmit Multiplexed Mode (Continued) Register 1 01BH 09BH 11BH 19BH 21BH 29BH 31BH 39BH Value (from Bit7 to Bit0) 00010000 00010000 00010000 00010000 00010000 00010000 00010000 00010000 Description 2
The FIFO is set to self-center its read pointer.
Note: 1. In the `Register' column, except for the Receive/Transmit Multiplexed mode, the register position of the Framer One is listed to represent the set of the registers of eight framers. The other registers position are tabulated in the `Register Map'. However, in Receive/Transmit Multiplexed mode, the register position of eight framers are all listed. 2. The `Description' illustrates the fundamental function of the operation mode. The others can be configured as desired.
4.2.4 OPERATION EXAMPLE In this chapter, some common operation examples are given for reference. 4.2.4.1 Using The HDLC Receiver In T1/J1 mode, the HDLC Receive can only be used in ESF format. Before using the HDLC#2 Receive, the TXCISEL (b3, T1/J1-00DH) must be set to 0 to enable the HDLC data link position for receive path. Since two HDLC Receive data links are integrated in one framer, one of the two HDLC Receive data links must be selected in the RHDLCSEL[1:0] (b7~6, T1/J1-00DH). The RHDLC #1 can only extract from F-bit of each odd frame. The RHDLC #2 can be set to extract from even and/or odd frames, from any channel, and from any bit. The follow is an example for selecting the HDLC Receive data link positions in RHDLC #2: a. to extract the HDLC data link from all bits of channel 20 of all framers in HDLC Receive #2: - set the TXCISEL (b3, T1/J1-00DH) to 0; - set the RHDLCSEL[1:0] (b7~6, T1/J1-00DH) to 01; - set the DL2_EVEN (b7, T1/J1-070H) to 1; - set the DL2_ODD (b6, T1/J1-070H) to 1; - set the DL2_TS[4:0] (b4~0, T1/J1-070H) to 10100; - set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to 11111111. After setting the HDLC data link position properly, the selected HDLC Receive should be enabled by setting the EN (b0, T1/J1-054H)to logic 1. If needed, set the MEN (b3, T1/J1-054H) and the MM (b2, T1/J1054H) to determine which Address Matching Mode to be selected (refer to Register Description for details). After setting these 3 bits, the RHDLC Primary Address Match register and the RHDLC Secondary Address Match register should be set to proper values. If the INTC[6:0] (b6~0, T1/J1-055H) are set, whenever the number of bytes in the RHDLC FIFO exceeds the value set in the INTC[6:0] (b6~0, T1/J1055H), the INTR (b0, T1/J1-056H) will be set to logic 1. This interrupt will persist until the RHDLC FIFO becomes empty. Setting the INTE (b7, T1/J1-055H) to logic 1 allows the internal interrupt status to be propagated to the INT output pin.
After setting these registers properly, the HDLC data can be received in a polled or interrupt driven mode. - Interrupt Driven Mode When the INTE (b7, T1/J1-055H) is set to logic 1, if the INT pin is asserted, the source of the interrupt should be identified firstly by reading the Interrupt ID register and Interrupt Source registers. If the source of the interrupt is HDLC Receive, the Interrupt Service procedure will be carried out as shown in Figure - 77. - Polling Mode In polling mode, the operation procedure is the same as Figure - 77, except that the entry of the service is from a local timer rather than an interrupt. To summarize the procedure of using HDLC Receive, a complete example is shown in Table - 54. Table - 54 . Example for Using HDLC Receiver Register Value 00DH 50H Description RHDLC #2 is selected. The HDLC Receive is accessable to the CPU interface. 070H C4H The TS4 of even frames and odd frames are selected. 071H FFH All the 8 bits are selected. 054H 0DH The function of the RHDLC #2 is enabled. Set the address match mode. 055H 8FH Set the INTE to 1. When the number of bytes in the RHDLC FIFO exceeds 15, an interrupt is generated. 058H 13H The primary address is set to 13H. 059H FFH The secondary address is set to FFH. Then read the data status in register 056H. Until a complete packet is received, read the data from register 057H .
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
INT asserts RHDLC interrupt N Other block interrupt service
Y Read RHDLC STATUS OVR=1 N COLS=1 N PKIN=1 Y PACKET COUNT * increment N Read RHDLC data Read RHDLC status OVR=1 N COLS=1 N PKIN=1 Y 000 N PBS[2:0]=? PACKET COUNT * increment Y Set EMPTY FIFO * flag Y Discard the last packet Y Set EMPTY FIFO * flag Y Discard the last packet
1XX Store this byte, decrement the PACKET COUNT *, check for CRC or non-integer number errors before deciding whether to keep the packet or not.
store the packet data 001 Discard this data byte, Set LINK ACTIVE * Flag 010
Discard this data byte , Clear LINK ACTIVE * Flag
N
FE=1 Y End of Interrupt service
Note: * The PACKET COUNT ,EMPTY FIFO and LINK ACTIVE is a local software variable
Figure - 77. Interrupt Service in T1/J1 Mode HDLC Receiver
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
4.2.4.2 Using The HDLC Transmitter In T1/J1 mode, the HDLC Transmit can only be used in ESF format. Before using the HDLC#2 Transmit, the TXCISEL (b3, T1/J1-00DH) must be set to 1 to enable the HDLC data link position for transmit path. Since two HDLC Transmit data links are integrated in one framer, one of the two HDLC Transmit data links must be selected in the THDLCSEL[1:0] (b5~4, T1/J1-00DH). The THDLC #1 can only insert to F-bit of each odd frame. The THDLC #2 can be set to insert to even and/ or odd frames, to any channel, and to any bit. The follow is an example for selecting the HDLC Transmit data link positions in THDLC #2: a. to insert the HDLC data link to all bits of channel 20 of all framers in HDLC Transmit #2: - set the TXCISEL (b3, T1/J1-00DH) to 1; - set the THDLCSEL[1:0] (b5~4, T1/J1-00DH) to 01; - set the DL2_EVEN (b7, T1/J1-070H) to 1; - set the DL2_ODD (b6, T1/J1-070H) to 1; - set the DL2_TS[4:0] (b4~0, T1/J1-070H) to 10100; - set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to 11111111. After setting the HDLC data link position properly, the selected HDLC Transmit should be enabled by setting the EN (b0, T1/J1-034H) to logic 1. The FIFOCLR (b6, T1/J1-034H) should be set and then cleared to initialize the THDLC FIFO. Set the CRC (b1, T1/J1-034H) to logic 1 if the Frame Check Sequences (FCS) generation is desired. Set the FULLE (b3, T1/J1037H), OVRE (b2, T1/J1-037H), UDRE (b1, T1/J1-037H) and LFILLE (b0, T1/J1-037H) to logic 1 if interrupt driven mode is used. Set THDLC Upper Transmit Threshold and THDLC Lower Transmit Threshold registers to the desired values. If a complete packet has been written into THDLC FIFO, the EOM (b3, T1/J1-034H) should be set. After setting these registers properly, the HDLC data can be transmitted in a polled or interrupt driven mode. - Interrupt Driven Mode Writing HDLC data to THDLC FIFO , the THDLC will transmit the HDLC data if the end of a packet was written or if the THDLC FIFO fill level reaches the Upper Transmit Threshold. The writing procedure is shown in Figure - 78. When the FULLE (b3, T1/J1-037H), OVRE (b2, T1/J1-037H), UDRE (b1, T1/J1-037H) and LFILLE (b0, T1/J1-037H) are set to logic 1, if the INT pin is asserted, the source of the interrupt should be identified firstly by reading the Interrupt ID register and Interrupt Source registers. If the source of the interrupt is HDLC Transmit, the Interrupt Service procedure will be carried out as shown in Figure - 79. - Polling Mode In packet transmission polling mode, the FULLE (b3, T1/J1-037H), OVRE (b2, T1/J1-037H), UDRE (b1, T1/J1-037H) and LFILLE (b0, T1/ J1-037H) should be set to logic 0. The THDLC Lower Transmit Threshold should be set to such a value that sufficient warning of an underrun is given. The procedure shown in Figure - 80 should be followed. To summarize the procedure of using HDLC Transmit, a complete example is shown in Table - 55.
THDLC Initial
Data is available
N
Y Write data into THDLC FIFO
End of packet Y Set EOM
N
Figure - 78. Writing Data to T1/J1 Mode THDLC FIFO
Table - 55. Example for Using HDLC Transmitter Register Value 00DH 58H 070H 071H 034H 034H 037H 039H 039H 039H 039H 039H 039H 039H 039H 034H C4H FFH C3H 83H 0FH 12H 34H 56H 78H 9AH BCH DEH FFH 8BH Description THDLC #2 is selected. The HDLC Transmit is accessable to the CPU interface. The TS4 of even frames and odd frames are selected. All the 8 bits are selected. The function of the THDLC #2 is enabled. The FCS is enables and the THDLC FIFO is reset. Enable the THDLC Interrupt Enable bits.
Write data into THDLC FIFO.
End of packet and set the EOM to 1.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
INT Asserts N Other Blocks Interrupt Service
THDLC Interrupt Y Y UNDRI=1 N Y OVRI=1 N FULLI=1 Set the RLP Flag 1 N LFILLI=1 Y BLFILL=1 Y End of packet Y Set EOM End of Interrupt Service N N N Y
FULL=1
Y N
Start a timer 2
Note: 1. RLP-Retransmit the last packet, a local software variable. 2. A local timer to wait for a certain time until the Full = 0 or the BLFILL = 1.
Figure - 79. Interrupt Service in T1/J1 Mode HDLC Transmitter
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
THDLC initial
Data is available Y Read THDLC interrupt status FULL=1 N
N
Y
Wait, Until FULL=0 or BBLFILL=1
Write the data into the THDLC FIFO Y More data to be tarnsmitted N Set EOM
Figure - 80. Polling Mode in T1/J1 Mode HDLC Transmitter
4.2.4.3 Using The PRBS Generator / Detector IDT82V2108 provide one PRBS generator/detector block to generate and detect an enormous variety of pseudo-random and repetitive patterns to diagnose T1/J1 data stream of eight framers. The common test patterns are tabulrized in Table - 56. The PRBS generator/detector block can be used to test T1/J1 line transmit-receive integrity and system backplane integrity. - Example For Testing T1/J1 Line Transmit-Receive Integrity Suppose to monitor the errors in Framer Two without taking the entire T1/J1 offline. Following procedure should be done. - Select Framer Two to be tested by the PRGD block; - Configure the PRGD register; - Chose a desired set of channels (for example CH2, CH4, CH5) for insert/extract PRGD test data; - Set the far end of the line to loop back at least the selected channels; - Monitor the T1/J1 line transmit-receive integrity. To realize the above function, the configuration in Table - 57 to Table 59 should be set. Table - 57 is the configuration for PRGD and loopback. Table - 58 shows the process to initialize the TPLC. Table - 59 shows the process to initialize the RPLC. After the above setting, read the 061H register twice. If the SYNCV (b4, T1/J1-061H) is logic 1 and the BEI (b2, T1/J1-061H) is logic 0, the pattern detector is in synchronization state.
Then insert errors into this link. Here suppose to insert 3 errors, then the configuration is shown in Table - 60. - Example For Testing T1/J1 System Backplane Integrity To test the T1/J1 system backplane integrity, the RXPATGEN (b2, T1/J1-00FH) should be set to logic 1 and the other registers are set as above. Then the PRGD can be used to test the system backplane integrity.
114
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 56. Test Pattern Pseudo-Random Pattern Generation (the PS [b4, T1/J1-060H] is logic 0) TR 1 LR 2 IR#1 3 IR#2 4 IR#3 5 IR#4 6 00 02 FF FF FF FF 00 03 FF FF FF FF 01 04 FF FF FF FF 04 05 FF FF FF FF 00 06 FF FF FF FF 03 06 FF FF FF FF 03 06 FF FF FF FF 04 08 FF FF FF FF 02 09 FF FF FF FF 08 0A FF FF FF FF 0D 0E FF FF FF FF 02 10 FF FF FF FF 06 11 FF FF FF FF 02 13 FF FF FF FF 01 14 FF FF FF FF 00 15 FF FF FF FF 11 16 FF FF FF FF 02 18 FF FF FF FF 02 1B FF FF FF FF 01 1C FF FF FF FF 02 1E FF FF FF FF Repetitive Pattern Generation (the PS [b4, T1/J1-060H] is logic 1) TR 1 LR 2 IR#1 3 IR#2 4 IR#3 5 IR#4 6 00 00 FF FF FF FF 00 00 FE FF FF FF 00 01 FE FF FF FF 00 03 FC FF FF FF 00 17 22 00 20 FF 00 0F 01 00 FF FF 00 07 01 FF FF FF 00 03 F1 FF FF FF 00 04 F0 FF FF 0F 00 02 FC FF FF FF
Pattern Type 2 3 -1 2 4 -1 2 5 -1 2 6 -1 2 7 -1 (Fractional T1 LB Activate) 2 7 -1 (Fractional T1 LB Activate) 2 7 -1 2 9 -1 (O.153) 2 10 -1 2 11 -1 (O.152,O.153) 2 15 -1 (O.151) 2 17 -1 2 18 -1 2 20 -1 (O.153) 2 21 -1 2 22 -1 2 23 -1 (O.151) 2 25 -1 2 28 -1 2 29 -1 2 31 -1
TINV 7 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0
RINV 7 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0
Pattern Type All ones All zeros Alternatingones/zeros Double alternatingones/zeros 3 in 24 1 in 16 1 in 8 1 in 4 DS1 Inbandloopback activate DS1 InbandLoopback deactivate
TINV 7 0 0 0 0 0 0 0 0 0 0
RINV 7 0 0 0 0 0 0 0 0 0 0
Note: 1. TR - Tap Register 2. LR - Shift Register Length Register 3. IR#1 - PRGD Pattern Insertion #1 Register 4. IR#2 - PRGD Pattern Insertion #2 Register 5. IR#3 - PRGD Pattern Insertion #3 Register 6. IR#4 - PRGD Pattern Insertion #4 Register 7. TINV, RINV - contained in the PRGD Control register
115
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 57. The Setting of PRGD Register Value Description 00FH 20H Select Framer 2 to be tested by the PRGD block. The PRGD pattern is inserted in the TPLC and detected in the RPLC. 060H 82H Set Pattern Detector registers as error counter register. Enable automatic resynchronization. 062H 18H Set the pattern length. 063H 02H Set the feedback tap position. 068H FFH Set the Pattern Insertion registers. 06BH FFH Load the data in the Pattern Insertion registers to generate the pattern. 08AH 04H Set diagnostic digital loopback mode. 0B0H 01H Enable the TPLC indirect registers to be accessable. 0D0H 01H Enable the RPLC indirect registers to be accessable. Table - 58. Initializtion of TPLC Register 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H Value 00H 01H 00H 02H 00H 03H 00H 04H 00H 05H 00H 06H 00H 07H 00H 08H 00H 09H 00H 0AH 00H 0BH 00H 0CH 00H 0DH 00H 0EH 00H
Table - 58. Initializtion of TPLC (Continued) Register 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H
116
Value 0FH 00H 10H 00H 11H 00H 12H 00H 13H 00H 14H 00H 15H 00H 16H 00H 17H 00H 18H 00H 31H 00H 32H 00H 33H 00H 34H 00H 35H 00H 36H 00H 37H 00H 38H 00H 39H 00H 3AH 00H 3BH 00H 3CH 00H 3DH 00H 3EH 00H
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 58. Initializtion of TPLC (Continued) Register 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H Value 3FH 00H 40H 00H 41H 00H 42H 00H 43H 00H 44H 00H 45H 00H 46H 00H 47H 00H 48H
Table - 59. Initializtion of RPLC (Continued) Register 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H Value 00H 08H 00H 09H 00H 0AH 00H 0BH 00H 0CH 00H 0DH 00H 0EH 00H 0FH 00H 10H 00H 11H 00H 12H 00H 13H 00H 14H 00H 15H 00H 16H 00H 17H 00H 18H
Then set the TEST in TPLC Payload Control register for CH2, CH4 and CH5. The process is: Register Value Description 0B3H 08H Set the TEST in TPLC Payload Control register 0B2H 02H for CH2. 0B3H 08H Set the TEST in TPLC Payload Control register 0B2H 04H for CH4. 0B3H 08H Set the TEST in TPLC Payload Control register 0B2H 05H for CH5. Table - 59. Initializtion of RPLC Register 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H Value 00H 01H 00H 02H 00H 03H 00H 04H 00H 05H 00H 06H 00H 07H
Then set the TEST in RPLC Payload Control register for CH2, CH4 and CH5. The process is: Register Value Description 0D3H 08H Set the TEST in RPLC Payload Control 0D2H 02H register for CH2. 0D3H 08H Set the TEST in RPLC Payload Control 0D2H 04H register for CH4 0D3H 08H Set the TEST in RPLC Payload Control 0D2H 05H register for CH5
117
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 60. Error Insertion Register 064H 064H 064H 064H 064H 064H Value 08H 00H 08H 00H 08H 00H
Set PCCE=1
BUSY=0 Y
N
Data are set in the Channel Indirect Data Buffer Register RWB=0 and address is specified in the Channel Indirect Address/ Control Register.
Then write 00H into the 06CH register to update the error counter registers. Then read the registers from 06CH to 06FH to check the error numbers.
Y
4.2.4.4 Using Payload Control and Receive CAS/RBS Buffer Before using the Receive/Transmit Payload Control and Receive CAS/RBS Buffer, the indirect registers of these blocks must be initialized to eliminate erroneous control data. The the PCCE (b0, T1/J1-050H & b0, T1/J1-030H & b0, T1/J1-040H) of these blocks must be set to logic 1 to enable these blocks. Then the BUSY (b7, T1/J1-051H & b7, T1/J1-031H & b7, T1/J1041H) must be checked before a new access request to the RPLC, TPLC and RCRB indirect registers. When the BUSY is logic 0, the new reading and writing access operations can be performed. Figure - 81 shows the writing sequence of the RPLC, TPLC and RCRB indirect registers. Figure - 82 shows the reading sequence of the RPLC, TPLC and RCRB indirect registers. 4.2.4.5 Using TJAT / Timing Option In different operation modes, the Timing Options and Clock Divisor Control registers can be set as the follows: - Transmit Clock Slave Mode (System Backplane Rate: 1.544M bit/s) The TSCCKA or TSCCKB is selected as the TJAT DPLL input reference clock. The TSCCKA and TSCCKB are both equal to 1.544M. The N1 (b7~0, T1/J1-019H) and N2 (b7~0, T1/J1-01AH) are set to their default value (2FH). The smoothed clock output from the TJAT is selected as the LTCK. - Transmit Clock Slave Mode (System Backplane Rate: 2.048M bit/s) The TSCCKA or TSCCKB is selected as the TJAT DPLL input reference clock. The TSCCKA and TSCCKB are both equal to 2.048M. The N1 (b7~0, T1/J1-019H) is set to `b11111111 and the N2 (b7~0, T1/J101AH) is set to `b11000000. The smoothed clock output from the TJAT is selected as the LTCK. - Transmit Clock Slave Mode (System Backplane Rate: 4.096M bit/s) The TSCCKA is selected as the TJAT DPLL input reference clock. The TSCCKA is equal to 2.048M. The N1 (b7~0, T1/J1-019H) is set to `b11111111 and the N2 (b7~0, T1/J1-01AH) is set to `b11000000. The smoothed clock output from the TJAT is selected as the LTCK.
More data to be written N End
Figure - 81. Writing Sequence of Indirect Register in T1/J1 Mode
Set PCCE=1 N
BUSY=0
Y RWB=1 and address is specified in the Channel Indirect Address/ Control Register. N
BUSY=0 Y
Read Channel Indirect Data Buffer Register Y
More data to be read N End
Figure - 82. Reading Sequence of Indirect Register in T1/J1 Mode
118
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
- Transmit Clock Master Mode The XCK/24 is selected as the TJAT DPLL input reference clock. The XCK/24 is selected as the LTCK. - Transmit Multiplexed Mode (System Backplane Rate: 8.192M bit/s) The TSCCKA is selected as the TJAT DPLL input reference clock. The TSCCKA is equal to 2.048M. The N1 (b7~0, T1/J1-019H) is set to `b11111111 and the N2 (b7~0, T1/J1-01AH) is set to `b11000000. The smoothed clock output from the TJAT is selected as the LTCK. - Transmit Multiplexed Mode (System Backplane Rate: 16.384M bit/s) The TSCCKA or TSCCKA/8 is selected as the TJAT DPLL input reference clock. The TSCCKA is equal to 2.048M or 16.384M. The N1 (b7~0, T1/J1-019H) is set to `b11111111 and the N2 (b7~0, T1/J1-01AH) is set to `b11000000. The smoothed clock output from the TJAT is selected as the LTCK.
5
The Micro-Processor Interface provides the logic to connect the microprocessor interface. For all accesses, CS must be low. The data bus and address bus of the interface can work in multiplexed on nonmultiplexed mode. In non-multiplexed mode, ALE pin should be connected to high. In multiplexed mode, data bus and address bus should be externally connected.
PROGRAMMING INFORMATION
5.1
REGISTER MAP
The registers are devided into two parts: E1 part and T1/J1 part. Before operation, the TEMODE (b0, 400H) must be set to specify which part to be accessed by the microprocessor. Table - 61. T1/E1 Mode Selection Register Address 400 Register T1 / E1 Mode Selection
119
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
5.1.1 E1 MODE REGISTER MAP When the TEMODE (b0, 400H) is logic 0, the E1 mode registers are accessed. Table - 62a. E1 Mode Register Map - Direct Register E1 Address Framer 1 Framer 2 Framer 3 Framer4 Framer 5 Framer 6 Framer 7 Framer8 000 080 100 180 200 280 300 380 001 081 101 181 201 281 301 381 002 082 102 182 202 282 302 382 003 083 103 183 203 283 303 383 004 084 104 184 204 284 304 384 005 085 105 185 205 285 305 385 006 086 106 186 206 286 306 386 007 087 107 187 207 287 307 387 008 088 108 188 208 288 308 388 009 00A 08A 10A 18A 20A 28A 30A 38A 00B 00C 00D 08D 10D 18D 20D 28D 30D 38D 00E 08E 10E 18E 20E 28E 30E 38E 00F 08F 10F 18F 20F 28F 30F 38F 010 090 110 190 210 290 310 390 011 091 111 191 211 291 311 391 012 092 112 192 212 292 312 392 013 093 113 193 213 293 313 393 014 094 114 194 214 294 314 394 015~017 095~097 115~117 195~197 215~217 295~297 315~317 395~397 018 098 118 198 218 298 318 398 019 099 119 199 219 299 319 399 01A 09A 11A 19A 21A 29A 31A 39A 01B 09B 11B 19B 21B 29B 31B 39B 01C 09C 11C 19C 21C 29C 31C 39C 01D~01F 09D~09F 11D~11F 19D~19F 21D~21F 29D~29F 31D~31F 39D~39F 020 0A0 120 1A0 220 2A0 320 3A0 021 0A1 121 1A1 221 2A1 321 3A1 022 0A2 122 1A2 222 2A2 322 3A2 023 0A3 123 1A3 223 2A3 323 3A3 024 0A4 124 1A4 224 2A4 324 3A4 025 0A5 125 1A5 225 2A5 325 3A5 026 0A6 126 1A6 226 2A6 326 3A6 027 0A7 127 1A7 227 2A7 327 3A7 028 0A8 128 1A8 228 2A8 328 3A8 029 02A 0A9 0AA 129 12A 1A9 1AA 229 22A 2A9 2AA 329 32A 3A9 3AA Register Receive Path Line Options Receive Side System Interface Options Transmit Path Configuration Transmit Side System Interface Options Transmit Timing Options Interrupt Source #1 Interrupt Source #2 Diagnostic Reserved Chip ID/ Global PMON Update HDLC Micro Select/Framer Reset Framer Interrupt ID PRGD Positioning/control Clock Monitor Receive Path Frame Pulse Configuration Reserved RESI Configuration RESI Frame Pulse Configuration RESI Parity Configuration RESI Timeslot Offset RESI Bit Offset Reserved TRSI Configuration TRSI Frame Pulse Configuration TRSI Parity Configuration and Status TRSI Timeslot Offset TRSI Bit Offset Reserved RJAT Interrupt Status RJAT Reference Clock Divisor(N1) RJAT Reference Clock Divisor(N2) RJAT Configuration TJAT Interrupt Status TJAT Reference Clock Divisor(N1) TJAT Reference Clock Divisor(N2) TJAT Configuration RHDLC 1(TXCISEL=0) Link Control/ THDLC 1(TXCISEL=1) Link Control RHDLC 1(TXCISEL=0) bits select/ THDLC 1(TXCISEL=1) bits select RHDLC 2(TXCISEL=0) Link Control/ THDLC 2(TXCISEL=1) Link Control
120
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 62a. E1 Mode Register Map - Direct Register (Continued) E1 Address Framer 1 Framer 2 Framer 3 Framer4 Framer 5 Framer 6 Framer 7 Framer8 02B 0AB 12B 1AB 22B 2AB 32B 3AB Register
RHDLC 2(TXCISEL=0) bits select/ THDLC 2(TXCISEL=1) bits select 02C 0AC 12C 1AC 22C 2AC 32C 3AC RHDLC 3(TXCISEL=0) Link Control/ THDLC 3(TXCISEL=1) Link Control 02D 0AD 12D 1AD 22D 2AD 32D 3AD RHDLC 3(TXCISEL=0) bits select/ THDLC 3(TXCISEL=1) bits select 02E~02F 0AE~0AF 12E~12F 1AE~1AF 22E~22F 2AE~2AF 32E~32F 3AE~3AF Reserved 030 0B0 130 1B0 230 2B0 330 3B0 FRMP Frame Alignment Option 031 0B1 131 1B1 231 2B1 331 3B1 FRMP Maintenance Mode Options 032 0B2 132 1B2 232 2B2 332 3B2 FRMP Framing Status Interrupt Enable 033 0B3 133 1B3 233 2B3 333 3B3 FRMP Maintenance/Alarm Status Interrupt Enable 034 0B4 134 1B4 234 2B4 334 3B4 FRMP Framing Status Interrupt Indication 035 0B5 135 1B5 235 2B5 335 3B5 FRMP Maintenance/Alarm Status Interrupt Indication 036 0B6 136 1B6 236 2B6 336 3B6 FRMP Framing Status 037 0B7 137 1B7 237 2B7 337 3B7 FRMP Maintenance/Alarm Status 038 0B8 138 1B8 238 2B8 338 3B8 FRMP TS0 International/National Bits 039 0B9 139 1B9 239 2B9 339 3B9 FRMP CRC Error Counter-LSB 03A 0BA 13A 1BA 23A 2BA 33A 3BA FRMP CRC Error Counter-MSB/TS16 Extra Bits 03B 0BB 13B 1BB 23B 2BB 33B 3BB FRMP National Bit Code-word Interrupt Enable 03C 0BC 13C 1BC 23C 2BC 33C 3BC FRMP National Bit Code-word Interrupts 03D 0BD 13D 1BD 23D 2BD 33D 3BD FRMP National Bit Code-word 03E 0BE 13E 1BE 23E 2BE 33E 3BE FRMP Frame pulse/Alarm/V5.2 Link ID Interrupt Enable 03F 0BF 13F 1BF 23F 2BF 33F 3BF FRMP Frame Pulse/Alarm Interrupts 040 0C0 140 1C0 240 2C0 340 3C0 FRMG Configuration 041 0C1 141 1C1 241 2C1 341 3C1 FRMG Alarm/Diagnostic Control 042 0C2 142 1C2 242 2C2 342 3C2 FRMG International Bits 043 0C3 143 1C3 243 2C3 343 3C3 FRMG Extra Bits 044 0C4 144 1C4 244 2C4 344 3C4 FRMG Interrupt Enable 045 0C5 145 1C5 245 2C5 345 3C5 FRMG Interrupt Status 046 0C6 146 1C6 246 2C6 346 3C6 FRMG National Bit Code-word Select 047 0C7 147 1C7 247 2C7 347 3C7 FRMG National Bit Code-word 048 0C8 148 1C8 248 2C8 348 3C8 RHDLC #1, 2, 3 Configuration 049 0C9 149 1C9 249 2C9 349 3C9 RHDLC #1, 2, 3 Interrupt Control 04A 0CA 14A 1CA 24A 2CA 34A 3CA RHDLC #1, 2, 3 Status 04B 0CB 14B 1CB 24B 2CB 34B 3CB RHDLC #1, 2, 3 Data 04C 0CC 14C 1CC 24C 2CC 34C 3CC RHDLC #1, 2, 3 Primary Address Match 04D 0CD 14D 1CD 24D 2CD 34D 3CD RHDLC #1, 2, 3 Secondary Address Match 04E~04F 0CE~0CF 14E~14F 1CE~1CF 24E~24F 2CE~2CF 34E~34F 3CE~3CF Reserved 050 0D0 150 1D0 250 2D0 350 3D0 THDLC #1, 2, 3 Configuration 051 0D1 151 1D1 251 2D1 351 3D1 THDLC #1, 2, 3 Upper Transmit Threshold 052 0D2 152 1D2 252 2D2 352 3D2 THDLC #1, 2, 3 Lower Transmit Threshold 053 0D3 153 1D3 253 2D3 353 3D3 THDLC #1, 2, 3 Interrupt Enable 054 0D4 154 1D4 254 2D4 354 3D4 THDLC #1, 2, 3 interrupt Status 055 0D5 155 1D5 255 2D5 355 3D5 THDLC #1, 2, 3 Transmit Data 056~058 0D6~0D8 156~158 1D6~1D8 256~258 2D6~2D8 356~358 3D6~3D8 Reserved 059 0D9 159 1D9 259 2D9 359 3D9 ELSB Interrupt Enable/ Status 05A 0DA 15A 1DA 25A 2DA 35A 3DA ELSB Idle Code
121
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 62a. E1 Mode Register Map - Direct Register (Continued) E1 Address Framer 1 Framer 2 Framer 3 Framer4 Framer 5 Framer 6 Framer 7 Framer8 05B 0DB 15B 1DB 25B 2DB 35B 3DB 05C 0DC 15C 1DC 25C 2DC 35C 3DC 05D 0DD 15D 1DD 25D 2DD 35D 3DD 05E 0DE 15E 1DE 25E 2DE 35E 3DE 05F 0DF 15F 1DF 25F 2DF 35F 3DF 060 0E0 160 1E0 260 2E0 360 3E0 061 0E1 161 1E1 261 2E1 361 3E1 062 0E2 162 1E2 262 2E2 362 3E2 063 0E3 163 1E3 263 2E3 363 3E3 064 0E4 164 1E4 264 2E4 364 3E4 Register
Reserved RPLC Configuration RPLC P Access Status RPLC Channel indirect Address/Control RPLC Channel Indirect Data Buffer TPLC Configuration TPLC P Access Status TPLC Channel indirect Address/Control TPLC Channel Indirect Data Buffer RCRB Configuration (COSS=0) / RCRB COSS[30:25] (COSS=1) 065 0E5 165 1E5 265 2E5 365 3E5 RCRB P Access Status (COSS=0) / RCRB COSS[24:17] (COSS=1) 066 0E6 166 1E6 266 2E6 366 3E6 RCRB CH IND Addr/Control (COSS=0) / RCRB COSS[16:9] (COSS=1) 067 0E7 167 1E7 267 2E7 367 3E7 RCRB CH Indirect Data Buffer (COSS=0) / RCRB COSS[8:1] (COSS=1) 068 0E8 168 1E8 268 2E8 368 3E8 PMON Interrupt Enable/Status 069 0E9 169 1E9 269 2E9 369 3E9 PMON FER Count 06A 0EA 16A 1EA 26A 2EA 36A 3EA PMON FEBE Count (LSB) 06B 0EB 16B 1EB 26B 2EB 36B 3EB PMON FEBE Count (MSB) 06C 0EC 16C 1EC 26C 2EC 36C 3EC PMON CRC Count (LSB) 06D 0ED 16D 1ED 26D 2ED 36D 3ED PMON CRC Count (MSB) 06E~06F 0EE~0EF 16E~16F 1EE~1EF 26E~26F 2EE~2EF 36E~36F 3EE~3EF Reserved 070 PRGD Control 071 PRGD Interrupt Enable/Status 072 PRGD Shift Register Length 073 PRGD Tap 074 PRGD Error Insertion 075 ~ 077 Reserved 078 PRGD Pattern Insertion #1 079 PRGD Pattern Insertion #2 07A PRGD Pattern Insertion #3 07B PRGD Pattern Insertion #4 07C PRGD Pattern Detector #1 07D PRGD Pattern Detector #2 07E PRGD Pattern Detector #3 07F PRGD Pattern Detector #4
122
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 62b. E1 Mode Register Map - Indirect Register Address 20-3FH 40-5FH 61-7FH 20-3FH 40-5FH 61-7FH 01-1FH / 21-3FH 41-5FH Register Payload control byte for TS0 to TS 31 Data trunk conditioning code for TS0 to TS31 Signaling trunk conditioning code for TS1 to TS31 Payload control byte for TS0 to TS 31 Idle code for TS0 to TS31 Signaling control byte for TS1 to TS31 Signaling data for TS1 to TS31 Signaling control for TS1 to TS31
RPLC Indirect Registers TPLC Indirect Registers RCRB Indirect Registers
5.1.2 T1 / J1 MODE REGISTER MAP When the TEMODE (b0, 400H) is logic 1, the T1/J1 mode registers are accessed. Table - 63a. T1/J1 Mode Register Map - Direct Register T1 / J1 Address Framer 1 Framer 2 Framer 3 Framer4 Framer 5 Framer 6 Framer 7 Framer8 000 080 100 180 200 280 300 380 001 081 101 181 201 281 301 381 002 082 102 182 202 282 302 382 003 083 103 183 203 283 303 383 004 084 104 184 204 284 304 384 005 085 105 185 205 285 305 385 006 086 106 186 206 286 306 386 007 087 107 187 207 287 307 387 008 088 108 188 208 288 308 388 009 089 109 189 209 289 309 389 00A 08A 10A 18A 20A 28A 30A 38A 00B 00C 00D 08D 10D 18D 20D 28D 30D 38D 00E 00F 010 090 110 190 210 29F 310 390 011 091 111 191 211 291 311 391 012 092 112 192 212 292 312 392 013 093 113 193 213 293 313 393 014 094 114 194 214 294 314 394 015 095 115 195 215 295 315 395 016~017 096~097 116~117 196~197 216~217 296~297 316~317 396~397 018 098 118 198 218 298 318 398 019 099 119 199 219 299 319 399 01A 09A 11A 19A 21A 29A 31A 39A 01B 09B 11B 19B 21B 29B 31B 39B 01C 09C 11C 19C 21C 29C 31C 39C 01D 09D 11D 19D 21D 29D 31D 39D
123
Register Receive Line Options Receive Side System Interface Options Back-plane Parity configuration/Status Receive Interface Configuration Transmit Interface Configuration Transmit Side System Interface Options Transmit Framing and Bypass Options Transmit Timing Options Interrupt Source #1 Interrupt Source #2 Diagnostic Reserved Chip ID/ Global PMON Update HDLC Micro Select/Framer Reset Framer Interrupt ID PRGD Positioning/control RJAT Interrupt Status RJAT Reference Clock Divisor(N1) RJAT Reference Clock Divisor(N2) RJAT Configuration TRSI Timeslot Offset TRSI Bit Offset Reserved TJAT Interrupt Status TJAT Reference Clock Divisor(N1) TJAT Reference Clock Divisor(N2) TJAT Configuration Reserved ELSB Interrupt Enable/ Status
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 63a. T1/J1 Mode Register Map - Direct Register (Continued) T1 / J1 Address Framer 3 Framer4 Framer 5 Framer 6 11E 19E 21E 29E 11F 19F 21F 29F 120 1A0 220 2A0 121 1A1 221 2A1 122 1A2 222 2A2 123~126 1A3~1A6 223~226 2A3~2A6 127 1A7 227 2A7 128~129 1A8~1A9 228~229 2A8~2A9 12A 1AA 22A 2AA 12B 1AB 22B 2AB 12C 1AC 22C 2AC 12D 1AD 22D 2AD 121 1A1 221 2A1 12F 1AF 22F 2AF 130 1B0 230 2B0 131 1B1 231 2B1 132 1B2 232 2B2 133 1B3 233 2B3 134 1B4 234 2B4 135 1B5 235 2B5 136 1B6 236 2B6 137 1B7 237 2B7 138 1B8 238 2B8 139 1B9 239 2B9 13A~13B 1BA~1BB 23A~23B 2BA~2BB 13C 1BC 23C 2BC 13D 1BD 23D 2BD 13E 1BE 23E 2BE 13F 1BF 23F 2BF 140 1C0 240 2C0 141 142 143 144 145 146 147 148 149 14A 14B 14C 14D 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 241 242 243 244 245 246 247 248 249 24A 24B 24C 24D 2C1 2C2 2C3 2C4 2C5 2C6 2C7 2C8 2C9 2CA 2CB 2CC 2CD Register Framer 7 Framer8 31E 39E 31F 39F 320 3A0 321 3A1 322 3A2 323~326 3A3~3A6 327 3A7 328~329 3A8~3A9 32A 3AA 32B 3AB 32C 3AC 32D 3AD 321 3A1 32F 3AF 330 3B0 331 3B1 332 3B2 333 3B3 334 3B4 335 3B5 336 3B6 337 3B7 338 3B8 339 3B9 33A~33B 3BA~3BB 33C 3BC 33D 3BD 33E 3BE 33F 3BF 340 3C0 341 342 343 344 345 346 347 348 349 34A 34B 34C 34D
124
Framer 1 Framer 2 01E 09E 01F 09F 020 0A0 021 0A1 022 0A2 023~026 0A3~0A6 027 0A7 028~029 0A8~0A9 02A 0AA 02B 0AB 02C 0AC 02D 0AD 02E 0AE 02F 0AF 030 0B0 031 0B1 032 0B2 033 0B3 034 0B4 035 0B5 036 0B6 037 0B7 038 0B8 039 0B9 03A~03B 0BA~0BB 03C 0BC 03D 0BD 03E 0BE 03F 0BF 040 0C0 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD
3C1 3C2 3C3 3C4 3C5 3C6 3C7 3C8 3C9 3CA 3CB 3CC 3CD
ELSB Idle Code Reserved T1 FRMP Configuration T1 FRMP interrupt enable T1 FRMP interrupt status Reserved Clock Monitor Reserved RBOM Configuration RBOM Code Status ALMD Configuration ALMD Interrupt Enable ALMD Interrupt Status ALMD Alarm Detection Status TPLC Configuration TPLC P Access Status TPLC Channel indirect Address/Control TPLC Channel Indirect Data Buffer THDLC #1, 2, 3 Configuration THDLC #1, 2, 3 Upper Transmit Threshold THDLC #1, 2, 3 Lower Transmit Threshold THDLC #1, 2, 3 Interrupt Enable THDLC #1, 2, 3 interrupt Status THDLC #1, 2, 3 Transmit Data Reserved IBCD Configuration IBCD Interrupt Enable/Status IBCD Active Code IBCD Deactivate Code RCRB Configuration (COSS=0) / RCRB COSS[30:25] (COSS=1) RCRB P Access Status (COSS=0) / RCRB COSS[24:17] (COSS=1) RCRB CH IND Addr/Control (COSS=0) / RCRB COSS[16:9] (COSS=1) RCRB CH Indirect Data Buffer (COSS=0) / RCRB COSS[8:1] (COSS=1) FRMG Configuration FRMG Alarm Transmit IBCG Configuration IBCG Loop-back Code Reserved PMON Interrupt Enable/Status PMON BEE Count (LSB) PMON BEE Count (MSB) PMON FER Count (LSB) PMON FER Count (MSB)
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
Table - 63a. T1/J1 Mode Register Map - Direct Register (Continued) T1 / J1 Address Framer 1 Framer 2 Framer 3 Framer4 Framer 5 Framer 6 Framer 7 Framer8 04E 0CE 14E 1CE 24E 2CE 34E 3CE 04F 0CF 14F 1CF 24F 2CF 34F 3CF 050 0D0 150 1D0 250 2D0 350 3D0 051 0D1 151 1D1 251 2D1 351 3D1 052 0D2 152 1D2 252 2D2 352 3D2 053 0D3 153 1D3 253 2D3 353 3D3 054 0D4 154 1D4 254 2D4 354 3D4 055 0D5 155 1D5 255 2D5 355 3D5 056 0D6 156 1D6 256 2D6 356 3D6 057 0D7 157 1D7 257 2D7 357 3D7 058 0D8 158 1D8 258 2D8 358 3D8 059 0D9 159 1D9 259 2D9 359 3D9 05A~05C 0DA~0DC 15A~15C 1DA~1DC 25A~25C 2DA~2DC 35A~35C 3DA~3DC 05D 0DD 15D 1DD 25D 2DD 35D 3DD 05E~05F 0DE~0DF 15E~15F 1DE~1DF 25E~25F 2DE~2DF 35E~35F 3DE~3DF 060 061 062 063 064 065 ~ 067 068 069 06A 06B 06C 06D 06E 06F 070 0F0 170 1F0 270 2F0 370 3F0 071 0F1 171 1F1 271 2F1 371 3F1 Register PMON OOF Count PMON COFA Count RPLC Configuration RPLC P Access Status RPLC Channel indirect Address/Control RPLC Channel Indirect Data Buffer RHDLC #1, 2, 3 Configuration RHDLC #1, 2, 3 Interrupt Control RHDLC #1, 2, 3 Status RHDLC #1, 2, 3 Data RHDLC #1, 2, 3 Primary Address Match RHDLC #1, 2, 3 Secondary Address Match Reserved TBOM Code Reserved PRGD Control PRGD Interrupt Enable/Status PRGD Shift Register Length PRGD Tap PRGD Error Insertion Reserved PRGD Pattern Insertion #1 PRGD Pattern Insertion #2 PRGD Pattern Insertion #3 PRGD Pattern Insertion #4 PRGD Pattern Detector #1 PRGD Pattern Detector #2 PRGD Pattern Detector #3 PRGD Pattern Detector #4 RHDLC 2(TXCISEL=0) Link Control / THDLC 2(TXCISEL=1) Link Control RHDLC 2(TXCISEL=0) bits select / THDLC 2(TXCISEL=1) bits select Reserved RESI Timeslot Offset RESI Bit Offset
072~076 0F2~0F6 172~176 1F2~1F6 272~276 2F2~0F6 372~376 3F2~3F6 077 0F7 177 1F7 277 2F7 377 3F7 078 0F8 178 1F8 278 2F8 378 3F8 Table - 63b. T1/J1 Mode Register Map - Indirect Register RPLC Indirect Register TPLC Indirect Register RCRB Indirect Register Address 01-18H 19-30H 31-48H 01-18H 19-30H 31-48H 01-18H / 21-38H 41-58H
125
Register Payload control byte for CH1 to CH24 Data trunk conditioning code for CH1 to CH24 Signaling trunk conditioning code for CH1 to CH24 Payload control byte for CH1 to CH24 Idle code for CH1 to CH24 Signaling control byte for CH1 to CH24 Signaling data for CH1 to CH24 Signaling control for CH1 to CH24
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
5.2
REGISTER DESCRIPTION
E1 Or T1 / J1 Mode Selection (400H) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 TEMODE R/W 1
TEMODE: This bit selects the operation mode globally for the chip. = 0: The chip operates in the E1 mode. = 1: The chip operates in the T1/J1 mode. 5.2.1 E1 MODE
E1 Receive Path Line Options (000H, 080H, 100H, 180H, 200H, 280H, 300H, 380H) Bit No. Bit Name Type Default 7 FIFOBYP R/W 0 6 UNF R/W 0 5 WORDERR R/W 0 4 CNTNFAS R/W 0 3 AUTOYELLOW R/W 0 2 AUTORED R/W 0 1 AUTOOOF R/W 0 0 AUTOUPDATE R/W 0
FIFOBYP: This bit decides whether the received data should pass through or bypass the Receive Jitter Attenuation FIFO. = 0: The received data pass through the RJAT FIFO. = 1: The RJAT FIFO is bypassed. The delay is reduced by typically 24 bits. UNF: = 0: The Frame Processor operates normally. = 1: Frame searching is disabled, the Receive CAS/RBS Buffer holds its signaling frozen, and Auto_OOF function, if enabled, will consider OOF to be declared. WORDERR, CNTNFAS: WORDERR CNTNFAS 0 0 1 0 0 1 1 1
Framing Bit Error Each bit error in a 7-bit FAS pattern is counted as a single framing bit error. One or more than one bit errors in a 7-bit FAS pattern is counted as a single framing bit error. Each bit error in a 7-bit FAS pattern is counted as a single framing bit error, and a logic 0 in the second bit of TS0 of NFAS is counted as a single bit error too. An 8-bit Error Word is consisted of a 7-bit FAS pattern and the second bit of timeslot 0 in the next NFAS frame. One or more than one bit errors in this 8-bit Error Word is counted as a single framing bit error.
AUTOYELLOW: This bit decides whether to send Yellow Alarm signal automatically. = 0: The automatic Yellow Alarm Transmission is disabled. It means that the RAI bit, the 3rd bit of NFAS frame, can only be transmitted when the REMAIS (b3, E1-041H) is set to 1. = 1: The automatic Yellow Alarm Transmission is enabled. It means that the RAI bit (the 3rd bit of NFAS frame) in the transmit data stream will be set to 1 automatically during loss of frame alignment or receiving AIS. The G706RAI (b0, E1-00EH) is used to select the conditions, under which the Yellow Alarm signal will be transmitted automatically. AUTORED: This bit decides whether to start trunk conditioning (replacing data on RSDn with the data stored in the data trunk conditioning registers in RPLC) automatically when Red Alarm is declared. = 0: The trunk conditioning is not activated automatically when RED (b3, E1-037 H) becomes 1. = 1: The trunk conditioning will be initiated automatically when the RED (b3, E1-037H) becomes 1.
126
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
AUTOOOF: This bit decides whether to start trunk conditioning (replacing data on RSDn with the data stored in the data trunk conditioning registers in RPLC) automatically in the duration of loss of basic frame. = 0: The trunk conditioning is not activated automatically when the OOFV (b6, E1-036 H) becomes 1. = 1: The trunk conditioning will be activated automatically when the OOFV (b6, E1-036 H) becomes 1. AUTOUPDATE: This bit decides whether the PMON and PRGD registers are automatically updated once every second. = 0: The PMON and PRGD registers are not automatically updated. They can only be updated by MCU operation. = 1: The PMON and PRGD registers will be automatically updated once every second. E1 Receive Side System Interface Options (001H, 081H, 101H, 181H, 201H, 281H, 301H, 381H) Bit No. Bit Name Type Default 7 LRCKFALL R/W 0 6 RSSIG_EN R/W 1 5 RSCKSEL R/W 0 4 MRBS R/W 0 3 MRBC R/W 0 2 OOSMFAIS R/W 0 1 TRKEN R/W 0 0 RXMTKC R/W 0
LRCKFALL: This bit selects the active edge of LRCKn to sample the data on the corresponding LRDn. = 0: the rising edge is selected. = 1: the falling edge is selected. RSSIG_EN: When Receive Clock Slave Mode is enabled (RSCKSLV = 1, b5, E1-010H), this bit configures the receive side system interface. = 0: the Receive Clock Slave RSCK Reference Mode is selected. The RSCKn/RSSIGn pin will be used as RSCKn to output a 2.048 MHz jitter attenuated version of LRCKn or an 8KHz clock. = 1: the Receive Clock Slave External Signaling mode is selected. The RSCKn/RSSIGn pin is used as RSSIGn to output the extracted signaling data. Each time-slot's signaling bits are timeslot aligned with the RSDn data stream and located in lower nibble (b5b6b7b8). RSCKSEL: When Receive Clock Slave RSCK Reference Mode is selected, this bit selects the frequency of the RSCKn. = 0: the RSCKn outputs an 8 KHz timing reference that is generated by dividing the jitter attenuated version of LRCKn. = 1: the RSCKn outputs a jitter attenuated version of the 2.048 MHz Line Receive Clock (LRCKn). MRBS: In Receive Multiplexed mode, this bit decides which bus the corresponding framer will use to output the received data. = 0: The first multiplexed bus (MRSD[1], MRSFS[1], MRSSIG[1]) is selected. = 1: The second multiplexed bus (MRSD[2], MRSFS[2], MRSSIG[2]) is selected. MRBC: This bit turns on or off the transmission of received data from the corresponding framer to the selected multiplexed receive bus. Users should complete the setting in the MRBS (b4, E1-001H) before enabling this bit. = 0: The corresponding framer will not output its data stream on the multiplexed bus. = 1: The corresponding framer will output its data stream on the multiplexed bus. OOSMFAIS: This bit decides whether to send Alarm Indication Signals (All Ones Signals) on RSSIGn to the system side in the condition of out of signaling multi-frame. This bit affects the corresponding timeslot of the MRSSIGn data stream if the multiplexed bus is enabled. = 0: The output on RSSIGn/MRSSIG pin will not be affected by the indication of out of Signaling Multi-Frame. = 1: The output on RSSIGn/MRSSIG pin will be set to all "1" in the condition of out of Signaling Multi-Frame.
127
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
TRKEN: This bit decides whether to substitute the data on RSDn with the contents in the ELSB Idle Code Register during out of Basic frame. After substitution, the ELSB Idle Code can still be overwritten by the contents in RPLC Data Trunk Conditioning Registers and Signaling Trunk Conditioning Registers on per timeslot basis. This bit only has effect in Receive Clock Slave mode, and it affects the corresponding timeslot of multiplexed bus MRSD when multiplexed bus operation is enabled. = 0: ELSB Idle Code Substitution is disabled. = 1: Data in all timeslots on the RSDn will be replaced by the contents in ELSB Idle Code Register during out of Basic frame. RXMTKC: This bit decides how to substitute the received data stream on RSDn and RSSIGn with the contents in the RPLC Data Trunk Conditioning Registers and the RPLC Signaling Trunk Conditioning Registers. This bit affects the corresponding timeslot of the MRSD and MRSSIG if the multiplexed backplane is enabled. = 0: The data and signaling are substituted on a per-timeslot basis in accordance with the control bits contained in the per-timeslot Payload Control Byte registers in the RPLC. = 1: the data on RSDn of all timeslots are replaced with the data contained in the Data Trunk Conditioning registers in RPLC, and the data on RSSIGn of all timeslots are replaced with the data contained in the Signaling Trunk Conditioning registers. To enable this function, the PCCE (b0, E105CH) of the RPLC must be set to logic 1. E1 Transmit Path Configuration (002H, 082H, 102H, 182H, 202H, 282H, 302H, 382H) Bit No. Bit Name Type Default 7 FIFOBYP R/W 0 6 TAISEN R/W 0 5 Reserved 4 PATHCRC R/W 0 3 Reserved 2 TSFSRISE R/W 0 1 Reserved 0 LTCKRISE R/W 0
FIFOBYP: This bit decides whether the transmit data should pass through or bypass the Transmit Jitter Attenuation FIFO. = 0: The transmit data pass through the TJAT FIFO. = 1: The TJAT FIFO is bypassed. The delay is reduced by typically 24 bits. TAISEN: This bit enables the line interface to generate an un-framed all-ones Alarm Indication Signal on the LTDn pin. = 0: normal operation. = 1: LTDn transmits all ones. PATHCRC: This bit allows upstream bit errors to be transmitted to the downstream transparently. When the data stream on TSDn is already in the CRC MultiFrame format, and the IDT82V2108 is going to change some bits in the data stream, this bit decides whether to replace the original CRC-4 bits with re-calculated CRC-4 bits or just modify the original CRC-4 bits according to the contribution caused by changing bits in the data stream. This bit only takes effect when the FPTYP (b1, E1-019H) is set to 1 and one of the INDIS (b1, E1-040H) or FDIS (b3, E1-045H) is set to 1. = 0: A new re-calculated CRC-4 value will overwrite the incoming CRC-4 word. As the new CRC-4 value is transmitted to downstream, the bit errors in upstream can not be detected by the downstream. = 1: The incoming CRC-4 value is modified to just reflect the bit changes made by IDT82V2108. If there is any bit error in the upstream, it will be transmitted to the downstream transparently, and the downstream machine can detect it. TSFSRISE: This bit selects the active edge of TSCCKB to update the Transmit Frame Pulse on TSFSn pin. = 0: the signal on TSFSn is updated on the falling edge of TSCCKB. = 1: the signal on TSFSn is updated on the rising edge of TSCCKB. LTCKRISE: This bit selects the active edge of LTCKn to update the data on LTDn. = 0: the data on LTDn pin is updated on the falling edge of LTCKn. = 1: the data on LTDn pin is updated on the rising edge of LTCKn.
128
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Transmit Side System Interface Options (003H, 083H, 103H, 183H, 203H, 283H, 303H, 383H) Bit No. Bit Name Type Default 7 Reserved 6 TSSIG_EN R/W 1 5 Reserved 4 MTBS R/W 0 3 2 Reserved 1 0
TSSIG_EN: In Transmit Clock Slave mode (TSCKSLV=1, b5, E1-018H), this bit configures the transmit side system interface. = 0: the Transmit Clock Slave TSFS Enable mode is selected. The TSFSn/TSSIGn pin is used as TSFSn output. = 1: the Transmit Clock Slave External Signaling mode is selected. The TSFSn/TSSIGn pin is used as TSSIGn input. In Transmit Multiplexed mode, this bit must be set to 1. MTBS: In Transmit Multiplexed mode, this bit selects which multiplexed bus will interface with the corresponding framer. = 0: The incoming data is taken from the first multiplexed bus (MTSD1, MTSSIG1). = 1: The incoming data is taken from the second multiplexed bus (MTSD2, MTSSIG2). E1 Transmit Timing Options (004H, 084H, 104H, 184H, 204H, 284H, 304H, 384H) Bit No. Bit Name Type Default 7 Reserved 6 5 4 3 2 1 0 TJATREF_SEL[2] TJATREF_SEL[1] TJATREF_SEL[0] LTCK_SEL[2] LTCK_SEL[1] LTCK_SEL[0] R/W R/W R/W R/W R/W R/W 1 0 0 1 0 1
TJATREF_SEL[2:0] - Transmit Jitter Attenuation DPLL Input Reference Clock Selection The TJATREF_SEL[2:0] select the input reference clock for the TJAT DPLL. TJATREF_SEL[2:0] Input Reference Clock 000 TSCCKA / 8 001 TSCCKB 010 LRCK 011 TSCCKA 100 XCK / 24 Others TSCCKB LTCK_SEL[2:0] - Line Transmit Clock (LTCKn) Selection LTCK_SEL[2:0] 000 001 010 011 100 Others
Line Transmit Clock TSCCKA / 8 TSCCKB LRCK TSCCKA XCK / 24 A smoothed clock output from the TJAT DPLL
129
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Interrupt Source #1 (005H, 085H, 105H, 185H, 205H, 285H, 305H, 385H) Bit No. Bit Name Type Default 7 PMON R X 6 FRMG R X 5 FRMP R X 4 PRGD R X 3 ELSB R X 2 RHDLC#1 R X 1 RHDLC#2 R X 0 RHDLC#3 R X
Bits in this register indicate which function block caused an interrupt signal on INT pin. Reading this register does not remove the interrupt indication. To remove the interrupt indication on the INT pin, the corresponding interrupt status register must be read. E1 Interrupt Source #2 (006H, 086H, 106H, 186H, 206H, 286H, 306H, 386H) Bit No. Bit Name Type Default 7 TRSI R X 6 Reserved 5 TJAT R X 4 RJAT R X 3 THDLC#1 R X 2 THDLC#2 R X 1 THDLC#3 R X 0 RCRB R X
Bits in this register indicate which function block caused an interrupt signal on INT pin. Reading this register does not remove the interrupt indication. To remove the interrupt indication on the INT pin, the corresponding interrupt status register must be read. E1 Diagnostics (007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 LINELB R/W 0 3 V52DIS R/W 0 2 DDLB R/W 0 1 RAIS R/W 0 0 TXDIS R/W 0
LINELB: Line Loop back means that the transmit line interface data and clock (LTDn and LTCKn) are internal directly comes from the received line data and clock (LRDn and LRCKn). The loop back data stream can pass through the Receive Jitter Attenuator or bypass the Receive Jitter Attenuator (if the Receive Jitter Attenuator is configured to be bypassed) = 0: Line loop back is disabled. = 1: Line loop back is enabled. V52DIS: = 0: All HDLC controllers of the corresponding framer are available to use. = 1: Only the first HDLC controller in receive direction (RHDLC#1) and transmit direction (THDLC#1) are available to use, the remaining HDLC controllers are disabled. Note that this bit can not be reset by software reset. It can only reset by hardware reset. DDLB: Digital Loop back means that the received line data and clock (LRDn and LRCKn) are internal directly comes from the transmit line data and clock (LTDn and LTCKn) without the Receive Jitter Attenuator. = 0: Digital loop back is disabled. = 1: Digital loop back is enabled RAIS: = 0: normal operation. = 1: force the data output on RSDn to be all ones, and freeze the signal on RSSIGn at the current valid signaling in Receive Clock Slave External Signaling mode. In Receive Multiplexed mode, the data of the corresponding framer output on MRSD is forced to be all ones, and the signal of the corresponding framer output on MRSSIG is frozen at the current valid signaling. TXDIS: = 0: normal transmission. = 1: force the data to be transmitted on the TLDn pin to be all zeros.
130
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Revision / Chip ID / Global PMON Update (009H) Bit No. Bit Name Type Default 7 TYPE[2] R 0 6 TYPE[1] R 0 5 TYPE[0] R 0 4 ID[4] R 0 3 ID[3] R 0 2 ID[2] R 0 1 ID[1] R 0 0 ID[0] R 1
Writing to this register causes all Performance Monitor and PRGD Generator/Detector counters to be updated simultaneously. TYPE[2:0]: TYPE[2:0] are fixed to 000, representing the IDT82V2108 chip. ID[4:0]: ID[4:0] are fixed to 00011, representing the current version number of the IDT82V2108. E1 Data Link Micro Select / Framer Reset (00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH) Bit No. Bit Name Type Default 7 6 5 4 RHDLCSEL[1] RHDLCSEL[0] THDLCSEL[1] THDLCSEL[0] R/W R/W R/W R/W X X X X 3 TXCISEL R/W X 2 Reserved 1 0 RESET R/W 0
RHDLCSEL[1:0]: The RHDLCSEL[1:0] select one of the three HDLC Receivers to be accessed by the microprocessor. At one time, the microprocessor can only access one HDLC controller. These bits must be set before using the HDLC controller. RHDLCSEL[1:0] the HDLC Receiver 00 RHDLC #1 01 RHDLC #2 10 RHDLC #3 11 Reserved THDLCSEL[1:0]: The THDLCSEL[1:0] select one of the three HDLC Transmitters to be accessed by the microprocessor. At one time, the microprocessor can only access one HDLC controller. These bits must be set before using the HDLC controller. THDLCSEL[1:0] the HDLC Transmitter 00 THDLC #1 01 THDLC #2 10 THDLC #3 11 Reserved TXCISEL: The registers addressed from E1-028H to E1-02DH are shared by the HDLC Receiver and HDLC Transmitter to decide the position of the extracted bit in the received data stream and the inserted bit in the transmitting data stream respectively. So this bit is used to decide whether the Read/Write operation on the registers addressed from E1-028H to E1-02DH is for the HDLC receiver or for the HDLC transmitter. = 0: the Read/Write operation on registers addressed from 028 H to 02D H is for HDLC receiver. = 1: the Read/Write operation on registers addressed from 028H to 02D H is for the HDLC transmitter. RESET: This bit implements a software reset for individual framer. = 0: normal operation. = 1: The corresponding framer is held in reset. However, this bit, the bits in this register and the V52DIS (b3, E1-007H) can not be reset. Therefor, a logic 0 must be written to bring the framer out of reset. Holding the framer in a reset state effectively puts it into a low power standby mode. A hardware reset clears the RESET bit, the bits in this register and the V52DIS (b3, E1-007H).
131
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Interrupt ID (00BH) Bit No. Bit Name Type Default 7 INT[8] R X 6 INT[7] R X 5 INT[6] R X 4 INT[5] R X 3 INT[4] R X 2 INT[3] R 0 1 INT[2] R 0 0 INT[1] R 0
This register indicates which one of the eight framers caused the interrupt INT pin to be logic low. When any one of the eight framers caused the interrupt, the corresponding bit in the INT[8:1] will be high. E1 Pattern Generator / Detector Positioning / Control (00CH) Bit No. Bit Name Type Default 7 PRGDSEL[2] R/W 0 6 PRGDSEL[1] R/W 0 5 PRGDSEL[0] R/W 0 4 Reserved 3 2 RXPATGEN R/W 0 1 UNF_GEN R/W 0 0 UNF_DET R/W 0
The IDT82V2108 has only one PRBS Generator/Detector (PRGD) shared by all the eight framers. At one time, only one framer can use this PRGD. This register selects which framer will use the PRGD and how the PRGD will be used. PRGDSEL[2:0]: PRGDSEL[2:0] select one of the eight framers to be tested by the PRGD block. PRGDSEL[2:0] Selected Framer 000 Framer 1 001 Framer 2 010 Framer 3 011 Framer 4 100 Framer 5 101 Framer 6 110 Framer 7 111 Framer 8 RXPATGEN: = 0: the pattern in PRGD is generated in the transmit path and is detected in the receive path. = 1: the pattern in PRGD is generated in the receive path and is detected in the transmit path. UNF_GEN: = 0: which timeslots of the selected path will be replaced by the PRGD pattern is specified in TPLC or RPLC. = 1: all the 32 timeslots of the selected path will be replaced by the PRGD pattern. UNF_DET: = 0: which timeslots of the selected path will be detected by PRGD pattern is specified in TPLC or RPLC. = 1: all the 32 timeslots of the selected path will be detected by PRGD pattern.
132
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Clock Monitor (00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 XCK R X 3 TSCCKB R X 2 TSCCKA R X 1 RSCCK R X 0 LRCK R X
This register provides activity monitoring on the IDT82V2108 clocks. When a monitored clock signal makes a low to high transition, the corresponding bit in this register is set to 1, and this bit remains to be 1 until this register is read. After a read operation on this register, all the bits in this register will be cleared to 0. A lack of transitions of the monitored clock will be indicated by 0 in the corresponding bit, which means that the clock fails. This register should be read periodically to detect clock failures. XCK: = 0: after the bit is read. = 1: a low to high transition occurs on the XCK. TSCCKB: = 0: after the bit is read. = 1: a low to high transition occurs on the TSCCKB. TSCCKA: = 0: after the bit is read. = 1: a low to high transition occurs on the TSCCKA. RSCCK: = 0: after the bit is read. = 1: a low to high transition occurs on the RSCCK. LRCK: = 0: after the bit is read. = 1: a low to high transition occurs on the LRCK. E1 Receive Path Frame Pulse Configuration (00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 2 PERTS_RSFS REF_MRSFS R/W R/W 0 0 1 OOCMFE0 R/W 0 0 G706RAI R/W 0
PERTS_RSFS, REF_MRSFS: PERTS_RSFS REF_MRSFS 0 0 1 0
the Pulse on the RSFSn/MRSFS The pulse output on the RSFS/MRSFS pin is forced to be logic 0. The signal on the RSFS/MRSFS pin is determined by the ROHM, BRXSMFP, BRCMFP and ALTIFP (b3b2b1b0, E1-011 H). X 1 RSFSn/MRSFS contains a reference frame pulse identical to the receive system side common frame pulse on the RSCFS/MRSCFS pin. In Receive Multiplexed mode, these two bits in the eight framers should be set in the same value.
OOCMFE0: This bit selects one of two operation modes concerning the transmission of E-bits when the framer is out of CRC-4 multiframe. = 0: transmit ones for the E-bits while out of CRC-4 Multi-Frame. = 1: transmit zeros for the E-bits while out of CRC-4 Multi-Frame. (This setting is compliant with the CRC-4 to non-CRC-4 interworking procedure in Annex B of G.706)
133
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
G706RAI: When the AUTOYELLOW (b3, E1-00H) is set as 1, which means the RAI bit will be transmitted automatically in certain conditions, this bit selects one of two criteria defining the conditions. If the AUTOYELLOW (b3, E1-00H) is 0, G706RAI does not have any effect. = 0: The RAI bit will be transmitted when out of Basic Frame, when AISD is declared, when CRC-4 to non-CRC-4 interworking is declared or when the off-line searching indicates out of Basic frame. This definition follows the ETSI standards. = 1: The RAI bit will be transmitted when out of Basic frame or when AISD is declared, but not when CRC-4 to non-CRC-4 interworking is declared nor when offline out-of frame is declared. This definition follows the Annex B of G.706. E1 Receive Backplane Configuration (010H, 090H, 110H, 190H, 210H, 290H, 310H, 390H) Bit No. Bit Name Type Default 7 FRACTN[1] R/W 0 6 FRACTN[0] R/W 0 5 RSCKSLV R/W 1 4 DE R/W 1 3 FE R/W 1 2 CMS R/W 0 1 RATE[1] R/W 0 0 RATE[0] R/W 0
FRACTN[1:0]: When Receive Clock Master mode is selected, (RSCKSLV=0, b5, E1-010H), these two bits selects one of the operation modes shown in the following table. The two bits will be ignored if the Receive Clock Slave mode is selected. (RSCKSLV=1, b5, E1-010H). FRACTN[1:0] Operation Mode 00 Receive Clock Master Full E1 mode 01 Reserved 10 Receive Clock Master Fractional E1 mode 11 Receive Clock Master Fractional E1 with F-bit mode "Full E1" mode means that the received entire frame (256 bits) is clocked out from RSDn pin, and there are no gaps in the RSCKn clock pulse. "Fractional E1" mode means that the RSCKn only clocks out on the selected time slots, and RSCKn does not pulse during those un-selected time slots. The time slots selection is decided by DTRKC/NxTS (b6, E1-RPLC-Indirect Register-20-3F H). "Fractional E1 with F-bit" mode is to support ITU recommendation G.802 where 1.544 Mbit/s data is carried within a 2.048 Mbit/s data stream. In this configuration, bits from the second bit of TS 26 to the last bit of the Basic Frame are suppressed, and the remaining bits can be selectively gapped by the DTRKC/NxTS (b6, E1-RPLC-Indirect Register-20-3F H). RSCKSLV: = 0: Receive Clock Master mode is selected. = 1: Received Clock Slave mode is selected. RSCKSLV must be set to 1 to support multiplexed backplane. DE: = 0: the signal on the RSDn and RSSIGn pins are updated on the falling edge of the RSCCK or the RSCK. = 1: the signal on the RSDn and RSSIG pins are updated on the rising edge of the RSCCK or the RSCK. In Receive Multiplexed mode, the DE in all eight framers should be set at the same value. FE: If FE is not equal to DE, the frame pulse will be sampled or updated one clock edge after the corresponding data pulse. = 0: the signal on the RSCFS pin is sampled or the signal on the RSFSn pin is updated on the falling edge of the RSCCK or the RSCKn. = 1: the signal on the RSCFS pin is sampled or the signal on the RSFSn pin is updated on the rising edge of the RSCCK or the RSCKn. In Receive Multiplexed mode, the FE in all eight framers should be set at the same value. CMS: = 0: the clock frequency of RSCCK/MRSCCK is the same as the bit rate of the backplane. = 1: the clock frequency of RSCCK/MRSCCK is the double of the bit rate of the backplane. The CMS of all eight framers should be set at the same value.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
RATE[1:0]: These bits determine the bit rate of the received data stream on the backplane. Note that to operate in the Receive Multiplexed mode, the RATE[1:0] in all eight framers should be configured to select the 8.192 Mbit/s backplane bit rate. When the RATE[1:0] selects the 8.192 Mbit/s, the RSCKSLV (b5, E1-010H) must be set to 1. RATE[1:0] Backplane Rate 00 Reserved 01 2.048M bit/s 10 Reserved 11 8.192M bit/s E1 Receive Backplane Frame Pulse Configuration (011H, 091H, 111H, 191H, 211H, 291H, 311H, 391H) Bit No. Bit Name Type Default 7 Reserved 6 FPINV R/W 0 5 FPMODE R/W 1 4 Reserved 3 ROHM R/W 0 2 BRXSMFP R/W 0 1 BRXCMFP R/W 0 0 ALTIFP R/W 0
FPINV: = 0: The framing pulse RSCFS and RSFSn/MRSFS are active high. = 1: The framing pulse RSCFS and RSFSn/MRSFS are active low. When this bit is used to indicate the active pulse for RSCFS or MRSFS, then it should be set to the same value for all eight framers. FPMODE: This bit decides whether to use RSCFS as the framing pulse or not. In Receive Clock Master mode (RSCKSLV=0, b5, E1-010H), the FPMODE must be 0. = 0: RSCFS/MRSCFS is unused. = 1: RSCFS/MRSCFS is used. In Receive Multiplexed mode, the FPMODE in all eight framers should be set to the same value. ROHM: When the PERTS_RSFS and the REF_MRSFS (b3~2, E1-00EH) are 1 and 0 respectively, this bit decides whether to use RSFSn pin to indicate TS0 and TS16. Details are tabulated in the following table. BRXSMFP, BRXCMFP: When the PERTS_RSFS and the REF_MRSFS (b3~2, E1-00EH) are 1 and 0 respectively, these two bits, together with the ALTIFP bit, select the output signal seen on the RSFSn pin. Details are tabulated in the following table. ALTIFP: When the RSFSn pin is configured to output the framing pulse for Basic Frame, Signaling Multiframe or CRC Multiframe, this bit permits suppression of every other framing pulse. The following table shows the details for the different configurations of RSFSn pin.
135
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
RSFSn / MRSFS Indication The RSFSn asserts for 1 bit cycle on the first bit of each Basic Frame output on the RSDn. The RSFSn asserts for 1 bit cycle on the first bit of every second Basic Frame output on the RSDn. 0 0 1 0 The RSFSn asserts for 1 bit cycle on the first bit of the first frame of each CRC Multi-Frame output on the RSDn (in case CRC Multi-Frame is disabled, the RSFSn asserts every 16 frames). 0 0 1 1 The RSFSn asserts for 1 bit cycle on the first bit of the first frame of every second CRC MultiFrame output on the RSDn (in case CRC Multi-Frame is disabled, the RSFSn asserts every 32 frames). 0 1 0 0 The RSFSn asserts for 1 bit cycle on the first bit of the first frame of each Signaling MultiFrame output on the RSDn (in case Signaling Multi-Frame is disabled, the RSFSn asserts every 16 frames). 0 1 0 1 The RSFSn asserts for 1 bit cycle on the first bit of the first frame of every second Signaling Multi-Frame output on the RSDn (in case Signaling Multi-Frame is disabled, the RSFSn asserts every 32 frames). 0 1 1 0 The RSFSn goes high/low at the start of the first bit of the first frame of each Signaling MultiFrame, and does the opposite at the end of the first bit of the first frame of each CRC MultiFrame. 0 1 1 1 The RSFSn goes high/low at the start of the first bit of the first frame of every second Signaling Multi-Frame, and does the opposite at the end of the first bit of the first frame of every second CRC Multi-Frame. 1 X X X The RSFSn pin pulses during the entire TS0 period and the entire TS16. In Receive Multiplexed mode, when the PERTS_RSFS and the REF_MRSFS (b3~2, E1-00EH) are 1 and 0 respectively, the MRSFS can only indicate the first bit of a Basic Frame of the selected first framer no matter what is set in the ROHM, BRXSMFP, BRXCMFP and ALTIFP.
ROHM 0 0
BRXSMFP 0 0
BRXCMFP 0 0
ALTIFP 0 1
136
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Receive Backplane Parity / F-bit Configuration (012H, 092H, 112H, 192H, 212H, 292H, 312H, 392H) Bit No. Bit Name Type Default 7 RPTYP R/W 0 6 RPTYE R/W 0 5 FIXF R/W 0 4 FIXPOL R/W 0 3 PTY_EXTD R/W 0 2 Reserved 1 TRI[1] R/W 0 0 TRI[0] R/W 0
RPTYP: This bit selects the parity type for the receive side system data. = 0: even parity is employed, which means a logic one should be inserted in the first bit of TS0 of each basic frame when the number of ones in the previous basic frame is odd. = 1: odd parity is employed, which means a logic one should be inserted in the first bit of TS0 of each basic frame when the number of ones in the previous basic frame is even. RPTYE: This bit enables the parity for the receive side system data. The bit is invalid in Receive Clock Master Fractional E1 (with F-bit) mode. = 0: disable the parity on the RSDn/MRSD pin. = 1: enable the parity on the RSDn/MRSD pin. FIXF: This bit controls whether the parity bit position is fixed at the level defined by the FIXPOL. It is invalid in Receive Clock Master Fractional E1 (with F-bit) mode and valid when RPTYE = 0. = 0: no action. = 1: the setting in the FIXPOL is valid. The first bit of TS0 of each basic frame output on the RSDn/MRSD pin is fixed with the value of FIXPOL. FIXPOL: This bit is invalid in Receive Clock Master Fractional E1 (with F-bit) mode and valid when the RPTYE = 0 and the FIXF = 1. = 0: force the first bit of TS0 of each basic frame output on the RSDn/MRSD pin to be logic 0. = 1: force the first bit of TS0 of each basic frame output on the RSDn/MRSD pin to be logic 1. PTY_EXTD: When the parity is calculated over the previous basic frame, the first bit of TS0 on the RSDn pin can be included or not. The decision is made by this bit. = 0: the first bit of TS0 on the RSDn/MRSD pin is not calculated. = 1: the first bit of TS0 on the RSDn/MRSD pin is calculated. TRI[1:0]: TRI[1:0] 00 10 01 11 Output Status on the RSDn/MRSD and RSSIGn/MRSSIG pin in high impedance Reserved normal output Reserved
137
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Receive Backplane Time Slot Offset (013H, 093H, 113H, 193H, 213H, 293H, 313H, 393H) Bit No. Bit Name Type Default 7 Reserved 6 TSOFF[6] R/W 0 5 TSOFF[5] R/W 0 4 TSOFF[4] R/W 0 3 TSOFF[3] R/W 0 2 TSOFF[2] R/W 0 1 TSOFF[1] R/W 0 0 TSOFF[0] R/W 0
These bits determine the timeslot offset between the signal on the RSCFS pin and the start of the Basic Frame output on the RSDn & RSSIGn pin. If the RSCFS does not exist, the timeslot offset is between the RSFSn and the start of the Basic Frame output on the RSDn & RSSIGn. In Receive Multiplexed mode, each framer contributes every fourth timeslot on MRSD[1:2] and MRSSIG[1:2]. They define a binary number. The offset can be set from 0 to 127 timeslots. E1 Receive Backplane Bit Offset (014H, 094H, 114H, 194H, 214H, 294H, 314H, 394H) Bit No. Bit Name Type Default 7 Reserved 6 5 4 RSD_RSCFS_EDGE R/W Reserved 0 3 BOFF_EN R/W 0 2 BOFF[2] R/W 0 1 BOFF[1] R/W 0 0 BOFF[0] R/W 0
RSD_RSCFS_EDGE: Valid when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is not equal to the FE (b3, E1-010H). = 0: select the second active edge of the RSCCK to update the signal on the RSDn, RSSIGn and RSFSn pins, or select the first active edge of the MRSCCK to update the signal on the MRSD, MRSSIG and MRSFS pins. = 1: select the first active edge of the RSCCK to update the signal on the RSDn, RSSIGn and RSFSn pins, or select the second active edge of the MRSCCK to update the signal on the MRSD, MRSSIG and MRSFS pins. (The signal on the RSCFS/MRSCFS pin is always sampled on the first active edge.) In Receive Multiplexed mode, the RSD_RSCFS_EDGE in all eight framers should be set at the same value. When the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-010H) is equal to FE (b3, E1-010H), the signals on the RSDn/MRSD, RSSIGn/ MRSSIG and RSFSn/MRSFS pins are updated on the first active edge of the RSCCK/MRSCCK. BOFF_EN: Valid when the CMS (b2, E1-010H) is logic 0. = 0: disable the bit offset. = 1: enable the bit offset. BOFF[2:0]: Valid when the CMS (b2, E1-010H) is logic 0 and the BOFF_EN is logic 1. These bits define a binary number. The content in the BOFF[2:0] determines the bit offset between the signal on the RSCFS pin and the start of the Basic Frame output on the RSDn & RSSIGn pin. If the RSCFS does not exist, the timeslot offset is between the RSFSn and the start of the Basic Frame output on the RSDn & RSSIGn. It is also available in Receive Multiplexed mode. Programming of the Bit Offsets is consistent with the convention established by the Concentration Highway Interface (CHI) specification. Refer to the Functional Description for details.
138
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Transmit Backplane Configuration (018H, 098H, 118H, 198H, 218H, 298H, 318H, 398H) Bit No. Bit Name Type Default 7 Reserved 6 5 TSCKSLV R/W 1 4 DE R/W 1 3 FE R/W 1 2 CMS R/W 0 1 RATE[1] R/W 0 0 RATE[0] R/W 0
TSCKSLV: = 0: Transmit Clock Master mode is selected. = 1: Transmit Clock Slave mode or Transmit Multiplexed mode is selected. DE: = 0: the data on the TSDn/MTSD and TSSIGn/MTSSIG pins are sampled on the falling edge of the TSCCKB/MTSCCKB or the LTCKn. = 1: the data on the TSDn/MTSD and TSSIGn/MTSSIG pins are sampled on the rising edge of the TSCCKB/MTSCCKB or the LTCKn. In Transmit Multiplexed mode, the DE of the eight framers should be set to the same value. FE: Valid in Transmit Clock Slave mode and Transmit Multiplexed mode. = 0: the data on the TSCFS/MTSCFS pin is sampled on the falling edge of TSCCKB/MTSCCKB. = 1: the data on the TSCFS/MTSCFS pin is sampled on the rising edge of TSCCKB/MTSCCKB. In Transmit Multiplexed mode, the FE of the eight framers should be set to the same value. CMS: = 0: the clock rate of TSCCKB/MTSCCKB is the same as that of the backplane. = 1: the clock rate of TSCCKB/MTSCCKB is twice that of the backplane. The CMS of the eight framers should be set to the same value. RATE[1:0]: These bits determine the bit rate of the transmit data stream on the backplane. Note that if any of the eight framers selects the 8.192 Mbit/s backplane bit rate, the multiplxed bus will be enabled for the chip. When the RATE[1:0] selects the 8.192 Mbit/s, the TSCKSLV (b5, E1-018H) must be set to 1. RATE[1:0] Backplane Rate 00 Reserved 01 2.048M bit/s 10 Reserved 11 8.192M bit/s (valid to eight frames)
139
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Transmit Backplane Frame Pulse Configuration (019H, 099H, 119H, 199H, 219H, 299H, 319H, 399H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 FPINV R/W 0 2 Reserved 1 FPTYP R/W 0 0 Reserved
FPINV: = 0: the positive pulse on the TSCFS pin is valid. = 1: the negative pulse on the TSCFS pin is valid. The FPINV of the eight framers should be the same value. FPTYP: = 0: indicate that the signal on the TSCFS pin pulses during the first bit of each Basic Frame. = 1: indicate that the signal on the TSCFS pin asserts on the first bit of each Signaling Multi-Frame and asserts oppositely following the first bit of each CRC Multi-Frame. The FPTYP of the eight framers should be the same value. E1 Transmit Backplane Parity Configuration and Status (01AH, 09AH, 11AH, 19AH, 21AH, 29AH, 31AH, 39AH) Bit No. Bit Name Type Default 7 TPTYP R/W 0 6 TPTYE R/W 0 5 TDI R X 4 Reserved 3 PTY_EXTD R/W 0 2 1 Reserved 0
TPTYP: = 0: even parity is employed in the first bit of TS0 of each Basic Frame input from the TSDn/MTSD pin, which means a logic one is expected in the position when the number of ones in the previous Basic Frame is odd. = 1: odd parity is employed in the first bit of TS0 of each Basic Frame input from the TSDn/MTSD pin, which means a logic one is expected in the position when the number of ones in the previous Basic Frame is even. TPTYE: This bit decides whether to generate an interrupt when a parity error is detected on the TSDn/MTSD pin. = 0: No interrupt is generated when a parity error is detected on the TSDn/MTSD pin. = 1: An interrupt on the INT pin is generated when a parity error is detected on the TSDn/MTSD pin. TDI: This bit indicates the parity error detected on the TSDn/MTSD pin. = 0: no parity error is detected on the TSDn/MTSD pin. = 1: a parity error is detected on the TSDn/MTSD pin. This bit is cleared to 0 when it is read. PTY_EXTD: = 0: the parity checking is calculated over the previous basic frame, excluding the first bit of TS0 on the TSDn/MTSD pin. = 1: the parity checking is calculated over the previous basic frame, including the first bit of TS0 on the TSDn/MTSD pin.
140
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 Transmit Backplane Time Slot Offset (01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH) Bit No. Bit Name Type Default 7 Reserved 6 TSOFF[6] R/W 0 5 TSOFF[5] R/W 0 4 TSOFF[4] R/W 0 3 TSOFF[3] R/W 0 2 TSOFF[2] R/W 0 1 TSOFF[1] R/W 0 0 TSOFF[0] R/W 0
In Transmit Clock Slave mode, the content in the TSOFF[6:0] determines the timeslot offset between the TSCFS and the start of the Basic Frame transmitted on the TSDn & TSSIGn. In Transmit Multiplexed mode, the content in the TSOFF[6:0] determines the timeslot offset between the MTSCFS and the start of the Basic Frame transmitted on the MTSD & MTSSIG for the corresponding framer. In Transmit Clock Master mode, the timeslot offset is disabled, that is, the TSOFF[6:0] must be logic 0. The TSOFF[6:0] define a binary number. The offset can be set from 0 to 127 timeslots. E1 Transmit Backplane Bit Offset (01CH, 09CH, 11CH, 19CH, 21CH, 29CH, 31CH, 39CH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 COFF R/W 0 3 CHI R/W 0 2 BOFF[2] R/W 0 1 BOFF[1] R/W 0 0 BOFF[0] R/W 0
COFF: Valid when the CMS (b2, E1-018H) is logic 1. = 0: select the first active edge of the TSCCKB/MTSCCKB to sample the data on the TSDn/MTSD, TSSIGn/MTSSIG and to update the data on the TSFSn. = 1: select the second active edge of the TSCCKB/MTSCCKB to sample the data on the TSDn/MTSD, TSSIGn/MTSSIG and to update the data on the TSFSn. (The signal on the TSCFS/MTSCFS pin is always sampled on the first active edge.) CHI: This bit controls if the value in the BOFF[2:0] is the actual value or meets the Concentration Highway Interface (CHI) specification. = 0: disable the CHI specification. = 1: enable the CHI specification. BOFF[2:0]: In Transmit Clock Master mode, the content in the BOFF[2:0] determines the bit offset between the signal on the TSFSn and the start of the Basic Frame transmitted on the TSDn. In Transmit Clock Slave mode, the content in the BOFF[2:0] determines the bit offset between the TSCFS and the start of the Basic Frame transmitted on the TSDn & TSSIGn. In Transmit Multiplexed mode, the content in the BOFF[2:0] determines the bit offset between the MTSCFS and the start of the Basic Frame transmitted on the MTSD & MTSSIG. These bits define a binary number. When the CHI = 0, the setting in the BOFF[2:0] is their actual value (0 stands for 0 bit offset, 1 stands for 1 bit offset). When the CHI = 1, programming of the BOFF[2:0] is consistent with the convention established by the Concentration Highway Interface (CHI) specification. Refer to the Functional Description for details.
141
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RJAT Interrupt Status (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 1 OVRI R X 0 UNDI R X
OVRI: If data are still attempted to write into the FIFO when the FIFO is already full, the overwritten event will occur. = 0: the RJAT FIFO is not overwritten. = 1: the RJAT FIFO is overwritten. This bit is cleared to 0 when it is read. UNDI: If data are still attempted to read from the FIFO when the FIFO is already empty, the under-run event will occur. = 0: the RJAT FIFO is not under-run. = 1: the RJAT FIFO is under-run. This bit is cleared to 0 when it is read. E1 RJAT Reference Clock Divisor (N1) Control (021H, 0A1H, 121H, 1A1H, 221H, 2A1H, 321H, 3A1H) Bit No. Bit Name Type Default 7 N1[7] R/W 0 6 N1[6] R/W 0 5 N1[5] R/W 1 4 N1[4] R/W 0 3 N1[3] R/W 1 2 N1[2] R/W 1 1 N1[1] R/W 1 0 N1[0] R/W 1
These bits define a binary number. The (N1[7:0] + 1) is the divisor of the input reference clock, which is the ratio between the frequency of the input reference clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the RJAT. E1 RJAT Output Clock Divisor (N2) Control (022H, 0A2H, 122H, 1A2H, 222H, 2A2H, 322H, 3A2H) Bit No. Bit Name Type Default 7 N2[7] R/W 0 6 N2[6] R/W 0 5 N2[5] R/W 1 4 N2[4] R/W 0 3 N2[3] R/W 1 2 N2[2] R/W 1 1 N2[1] R/W 1 0 N2[0] R/W 1
These bits define a binary number. The (N2[7:0] + 1) is the divisor of the output smoothed clock, which is the ratio between the frequency of the output smoothed clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the RJAT.
142
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RJAT Configuration (023H, 0A3H, 123H, 1A3H, 223H, 2A3H, 323H, 3A3H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 CENT R/W 0 3 UNDE R/W 0 2 OVRE R/W 0 1 Reserved 0 LIMIT R/W 1
CENT: The CENT allows the RJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. = 0: disable the self-center. Data are pass through uncorrupted. = 1: enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full. A positive transition in this bit will execute a self-center action immediately. UNDE: This bit decides whether to generate an interrupt when the RJAT FIFO is under-run. = 0: No interrupt is generated when the RJAT FIFO is under-run. = 1: An interrupt on the INT pin is generated when the RJAT FIFO is under-run. OVRE: This bit decides whether to generate an interrupt when the RJAT FIFO is overwritten. = 0: No interrupt is generated when the RJAT FIFO is overwritten. = 1: An interrupt on the INT pin is generated when the RJAT FIFO is overwritten. LIMIT: = 0: disable the limitation of the jitter attenuation. = 1: enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift conditions. E1 TJAT Interrupt Status (024H, 0A4H, 124H, 1A4H, 224H, 2A4H, 324H, 3A4H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 1 OVRI R X 0 UNDI R X
OVRI: If data are still attempted to write into the FIFO when the FIFO is already full, the overwritten event will occur. = 0: the TJAT FIFO is not overwritten. = 1: the TJAT FIFO is overwritten. This bit is cleared to 0 when it is read. UNDI: If data are still attempted to read from the FIFO when the FIFO is already empty, the under-run event will occur. = 0: the TJAT FIFO is not under-run. = 1: the TJAT FIFO is under-run. This bit is cleared to 0 when it is read.
143
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 TJAT Reference Clock Divisor (N1) Control (025H, 0A5H, 125H, 1A5H, 225H, 2A5H, 325H, 3A5H) Bit No. Bit Name Type Default 7 N1[7] R/W 0 6 N1[6] R/W 0 5 N1[5] R/W 1 4 N1[4] R/W 0 3 N1[3] R/W 1 2 N1[2] R/W 1 1 N1[1] R/W 1 0 N1[0] R/W 1
These bits define a binary number. The (N1[7:0] + 1) is the divisor of the input reference clock, which is the ratio between the frequency of the input reference clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the TJAT. E1 TJAT Output Clock Divisor (N2) Control (026H, 0A6H, 126H, 1A6H, 226H, 2A6H, 326H, 3A6H) Bit No. Bit Name Type Default 7 N2[7] R/W 0 6 N2[6] R/W 0 5 N2[5] R/W 1 4 N2[4] R/W 0 3 N2[3] R/W 1 2 N2[2] R/W 1 1 N2[1] R/W 1 0 N2[0] R/W 1
These bits define a binary number. The (N2[7:0] + 1) is the divisor of the output smoothed clock, which is the ratio between the frequency of the output smoothed clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the TJAT. E1 TJAT Configuration (027H, 0A7H, 127H, 1A7H, 227H, 2A7H, 327H, 3A7H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 CENT R/W 0 3 UNDE R/W 0 2 OVRE R/W 0 1 Reserved 0 LIMIT R/W 1
CENT: The CENT allows the TJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. = 0: disable the self-center. Data are pass through uncorrupted. = 1: enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full. A positive transition in this bit will execute a self-center action immediately. UNDE: This bit decides whether to generate an interrupt when the TJAT FIFO is under-run. = 0: No interrupt is generated when the TJAT FIFO is under-run. = 1: An interrupt on the INT pin is generated when the TJAT FIFO is under-run. OVRE: This bit decides whether to generate an interrupt when the TJAT FIFO is overwritten. = 0: No interrupt is generated when the TJAT FIFO is overwritten. = 1: An interrupt on the INT pin is generated when the TJAT FIFO is overwritten. LIMIT: = 0: disable the limitation of the jitter attenuation. = 1: enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift conditions.
144
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RHDLC Receive Data Link 1 Control (TXCISEL = 0) (028H, 0A8H, 128H, 1A8H, 228H, 2A8H, 328H, 3A8H) Bit No. Bit Name Type Default 7 DL1_EVEN R/W 0 6 DL1_ODD R/W 0 5 TS16_EN R/W 1 4 DL1_TS[4] R/W 0 3 DL1_TS[3] R/W 0 2 DL1_TS[2] R/W 0 1 DL1_TS[1] R/W 0 0 DL1_TS[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 0, this register is used for the Receive HDLC #1. DL1_EVEN: = 0: the data is not extracted from the even frames. = 1: the data is extracted from the even frames. The even frames are FAS frames. DL1_ODD: = 0: the data is not extracted from the odd frames. = 1: the data is extracted from the odd frames. The odd frames are NFAS frames. TS16_EN: This bit is valid when the DL1_EVEN and DL1_ODD are both 0. = 0: the data is not extracted from the TS16. = 1: the data is extracted from the TS16. DL1_TS[4:0]: These bits represent the binary value of the timeslot to extract the data from. They are invalid when the DL1_EVEN and the DL1_ODD are both logic 0. E1 RHDLC Data Link 1 Bit Select (TXCISEL = 0) (029H, 0A9H, 129H, 1A9H, 229H, 2A9H, 329H, 3A9H) Bit No. Bit Name Type Default 7 DL1_BIT[7] R/W 0 6 DL1_BIT[6] R/W 0 5 DL1_BIT[5] R/W 0 4 DL1_BIT[4] R/W 0 3 DL1_BIT[3] R/W 0 2 DL1_BIT[2] R/W 0 1 DL1_BIT[1] R/W 0 0 DL1_BIT[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 0, this register is used for the Receive HDLC #1. DL1_BITn: = 0: the data is not extracted from the corresponding bit. = 1: the data is extracted from the corresponding bit of the assigned timeslot. These bits are invalid when the DL1_EVEN and the DL1_ODD are both logic 0. The DL1_BIT[7] corresponds to the first bit (MSB) of the selected timeslot.
145
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RHDLC Receive Data Link 2 Control (TXCISEL = 0) (02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH) Bit No. Bit Name Type Default 7 DL2_EVEN R/W 0 6 DL2_ODD R/W 0 5 Reserved 4 DL2_TS[4] R/W 0 3 DL2_TS[3] R/W 0 2 DL2_TS[2] R/W 0 1 DL2_TS[1] R/W 0 0 DL2_TS[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 0, this register is used for the Receive HDLC #2. DL2_EVEN: = 0: the data is not extracted from the even frames. = 1: the data is extracted from the even frames. The even frames are FAS frames. DL2_ODD: = 0: the data is not extracted from the odd frames. = 1: the data is extracted from the odd frames. The odd frames are NFAS frames. DL2_TS[4:0]: These bits represent the binary value of the timeslot to extract the data from. They are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. E1 RHDLC Data Link 2 Bit Select (TXCISEL = 0) (02BH, 0ABH, 12BH, 1ABH, 22BH, 2ABH, 32BH, 3ABH) Bit No. Bit Name Type Default 7 DL2_BIT[7] R/W 0 6 DL2_BIT[6] R/W 0 5 DL2_BIT[5] R/W 0 4 DL2_BIT[4] R/W 0 3 DL2_BIT[3] R/W 0 2 DL2_BIT[2] R/W 0 1 DL2_BIT[1] R/W 0 0 DL2_BIT[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 0, this register is used for the Receive HDLC #2. DL2_BITn: = 0: the data is not extracted from the corresponding bit. = 1: the data is extracted from the corresponding bit of the assigned timeslot. These bits are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. The DL2_BIT[7] corresponds to the first bit (MSB) of the selected timeslot.
146
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RHDLC Receive Data Link 3 Control (TXCISEL = 0) (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH) Bit No. Bit Name Type Default 7 DL3_EVEN R/W 0 6 DL3_ODD R/W 0 5 Reserved 4 DL3_TS[4] R/W 0 3 DL3_TS[3] R/W 0 2 DL3_TS[2] R/W 0 1 DL3_TS[1] R/W 0 0 DL3_TS[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 0, this register is used for the Receive HDLC #3. DL3_EVEN: = 0: the data is not extracted from the even frames. = 1: the data is extracted from the even frames. The even frames are FAS frames. DL3_ODD: = 0: the data is not extracted from the odd frames. = 1: the data is extracted from the odd frames. The odd frames are NFAS frames. DL3_TS[4:0]: These bits represent the binary value of the timeslot to extract the data from. They are invalid when the DL3_EVEN and the DL3_ODD are both logic 0. E1 RHDLC Data Link 3 Bit Select (TXCISEL = 0) (02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH) Bit No. Bit Name Type Default 7 DL3_BIT[7] R/W 0 6 DL3_BIT[6] R/W 0 5 DL3_BIT[5] R/W 0 4 DL3_BIT[4] R/W 0 3 DL3_BIT[3] R/W 0 2 DL3_BIT[2] R/W 0 1 DL3_BIT[1] R/W 0 0 DL3_BIT[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 0, this register is used for the Receive HDLC #3. DL3_BITn: = 0: the data is not extracted from the corresponding bit. = 1: the data is extracted from the corresponding bit of the assigned timeslot. These bits are invalid when the DL3_EVEN and the DL3_ODD are both logic 0. The DL3_BIT[7] corresponds to the first bit (MSB) of the selected timeslot.
147
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC Transmit Data Link 1 Control (TXCISEL = 1) (028H, 0A8H, 128H, 1A8H, 228H, 2A8H, 328H, 3A8H) Bit No. Bit Name Type Default 7 DL1_EVEN R/W 0 6 DL1_ODD R/W 0 5 TS16_EN R/W 1 4 DL1_TS[4] R/W 0 3 DL1_TS[3] R/W 0 2 DL1_TS[2] R/W 0 1 DL1_TS[1] R/W 0 0 DL1_TS[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 1, this register is used for the Transmit HDLC #1. DL1_EVEN: = 0: the data is not inserted to the even frames. = 1: the data is inserted to the even frames. The even frames are FAS frames. DL1_ODD: = 0: the data is not inserted to the odd frames. = 1: the data is inserted to the odd frames. The odd frames are NFAS frames. TS16_EN: This bit is valid when the DL1_EVEN and DL1_ODD are both 0 and the CCS is selected (the SIGEN [b6, E1-040H] and the DLEN [b5, E1-040H] are logic 1). = 0: the data is not inserted to the TS16. = 1: the data is inserted to the TS16. DL1_TS[4:0]: The data is inserted into the timeslot defined by the binary number in these bits. They are invalid when the DL1_EVEN and the DL1_ODD are both logic 0. E1 THDLC Data Link 1 Bit Select (TXCISEL = 1) (029H, 0A9H, 129H, 1A9H, 229H, 2A9H, 329H, 3A9H) Bit No. Bit Name Type Default 7 DL1_BIT[7] R/W 0 6 DL1_BIT[6] R/W 0 5 DL1_BIT[5] R/W 0 4 DL1_BIT[4] R/W 0 3 DL1_BIT[3] R/W 0 2 DL1_BIT[2] R/W 0 1 DL1_BIT[1] R/W 0 0 DL1_BIT[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 1, this register is used for the Transmit HDLC #1. DL1_BITn: = 0: the data is not inserted to the corresponding bit. = 1: the data is inserted to the corresponding bit of the assigned timeslot. These bits are invalid when the DL1_EVEN and the DL1_ODD are both logic 0. The DL1_BIT[7] corresponds to the first bit (MSB) of the selected timeslot.
148
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC Transmit Data Link 2 Control (TXCISEL = 1) (02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH) Bit No. Bit Name Type Default 7 DL2_EVEN R/W 0 6 DL2_ODD R/W 0 5 Reserved 4 DL2_TS[4] R/W 0 3 DL2_TS[3] R/W 0 2 DL2_TS[2] R/W 0 1 DL2_TS[1] R/W 0 0 DL2_TS[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 1, this register is used for the Transmit HDLC #2. DL2_EVEN: = 0: the data is not inserted to the even frames. = 1: the data is inserted to the even frames. The even frames are FAS frames. DL2_ODD: = 0: the data is not inserted to the odd frames. = 1: the data is inserted to the odd frames. The odd frames are NFAS frames. DL2_TS[4:0]: The data is inserted into the timeslot defined by the binary number in these bits. They are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. E1 THDLC Data Link 2 Bit Select (TXCISEL = 1) (02BH, 0ABH, 12BH, 1ABH, 22BH, 2ABH, 32BH, 3ABH) Bit No. Bit Name Type Default 7 DL2_BIT[7] R/W 0 6 DL2_BIT[6] R/W 0 5 DL2_BIT[5] R/W 0 4 DL2_BIT[4] R/W 0 3 DL2_BIT[3] R/W 0 2 DL2_BIT[2] R/W 0 1 DL2_BIT[1] R/W 0 0 DL2_BIT[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 1, this register is used for the Transmit HDLC #2. DL2_BITn: = 0: the data is not inserted to the corresponding bit. = 1: the data is inserted to the corresponding bit of the assigned timeslot. These bits are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. The DL2_BIT[7] corresponds to the first bit (MSB) of the selected timeslot.
149
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC Transmit Data Link 3 Control (TXCISEL = 1) (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH) Bit No. Bit Name Type Default 7 DL3_EVEN R/W 0 6 DL3_ODD R/W 0 5 Reserved 4 DL3_TS[4] R/W 0 3 DL3_TS[3] R/W 0 2 DL3_TS[2] R/W 0 1 DL3_TS[1] R/W 0 0 DL3_TS[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 1, this register is used for the Transmit HDLC #3. DL3_EVEN: = 0: the data is not inserted to the even frames. = 1: the data is inserted to the even frames. The even frames are FAS frames. DL3_ODD: = 0: the data is not inserted to the odd frames. = 1: the data is inserted to the odd frames. The odd frames are NFAS frames. DL3_TS[4:0]: The data is inserted into the timeslot defined by the binary number in these bits. They are invalid when the DL3_EVEN and the DL3_ODD are both logic 0. E1 THDLC Data Link 3 Bit Select (TXCISEL = 1) (02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH) Bit No. Bit Name Type Default 7 DL3_BIT[7] R/W 0 6 DL3_BIT[6] R/W 0 5 DL3_BIT[5] R/W 0 4 DL3_BIT[4] R/W 0 3 DL3_BIT[3] R/W 0 2 DL3_BIT[2] R/W 0 1 DL3_BIT[1] R/W 0 0 DL3_BIT[0] R/W 0
When the TXCISEL (b3, E1-00AH) is 1, this register is used for the Transmit HDLC #3. DL3_BITn: = 0: the data is not inserted to the corresponding bit. = 1: the data is inserted to the corresponding bit of the assigned timeslot. These bits are invalid when the DL3_EVEN and the DL3_ODD are both logic 0. The DL3_BIT[7] corresponds to the first bit (MSB) of the selected timeslot.
150
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Frame Alignment Options (030H, 0B0H, 130H, 1B0H, 230H, 2B0H, 330H, 3B0H) Bit No. Bit Name Type Default 7 CRCEN R/W 1 6 CASDIS R/W 0 5 C2NCIWCK R/W 0 4 Reserved 3 2 REFR R/W 0 1 REFCRCE R/W 1 0 REFRDIS R/W 0
CRCEN: = 0: disable searching for the CRC Multi-Frame. = 1: enable searching for the CRC Multi-Frame alignment signal and monitor the errors in the CRC Multi-Frame. CASDIS: = 0: enable searching for the Channel Associated Signaling (CAS) Multi-Frame alignment signal and monitor the errors in the Signaling MultiFrame. = 1: disable searching for the Channel Associated Signaling Multi-Frame. C2NCIWCK: = 0: stop searching for the CRC Multi-Frame alignment signal in CRC to non-CRC inter-working mode. = 1: continue searching for the CRC Multi-Frame alignment signal even if CRC to non-CRC inter-working has been declared. REFR: A transition from logic 0 to logic 1 forces to re-search for a new Basic Frame. REFCRCE: This bit decides if the Frame Processor re-searches for the Basic Frame when there are excessive CRC errors. The excessive CRC errors is defined as more than 914 CRC errors in one second. One CRC error is counted when the local calculated CRC-4 is not equal to the received CRC4. = 0: disable re-searching for the Basic Frame when there are excessive CRC errors. = 1: enable re-searching for the Basic Frame when there are excessive CRC errors. REFRDIS: 0 = enable re-searching for the Basic Frame when it is out of basic frame sync or there are excessive CRC errors. 1 = "locked in frame" once initial frame alignment has been found. Disable re-searching for the Basic Frame under any error conditions once the initial Basic Frame sync is acquired. While the FRMP remains locked in frame due to REFRDIS=1, a received AIS will not be detected since the Frame Processor must be out-offrame to detect AIS.
151
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Maintenance Mode Options (031H, 0B1H, 131H, 1B1H, 231H, 2B1H, 331H, 3B1H) Bit No. Bit Name Type Default 7 Reserved 6 BIT2C R/W 1 5 SMFASC R/W 0 4 TS16C R/W 0 3 RAIC R/W 0 2 Reserved 1 AISC R/W X 0 EXCRCERR R X
BIT2C: = 0: out of basic frame sync is declared on 3 consecutive FAS errors. = 1: enable the additional criteria to declare out of basic frame sync. Thus, out of basic frame sync is declared when 3 consecutive logic 0 are received in bit 2 of TS0 of NFAS or 3 consecutive FAS are in errors. SMFASC: = 0: enable the declaration of out of signaling multi-frame sync when 2 consecutive Signaling Multi-Frame alignment patterns have been received in error. = 1: enable the declaration of out of signaling multi-frame sync when 2 consecutive Signaling Multi-Frame alignment patterns have been received in error or when all the content in TS16 of Frame 0 are logic 0 for one or two consecutive multi-frames which is defined in TS16C (b4, E1-031H). TS16C: Valid when the SMFASC (b5, E1-031H) is logic 1. = 0: enable the declaration of out of signaling multi-frame sync when all the content in TS16 are logic 0 for one multi-frame. = 1: enable the declaration of out of signaling multi-frame sync when all the content in TS16 are logic 0 for two consecutive multi-frames. RAIC: = 0: set the RAIV (b7, E1-037H) to be logic 1 on the reception of any A bit being logic one, and set the RAIV (b7, E1-037H) to be logic 0 on the reception of any A bit being logic zero. = 1: set the RAIV (b7, E1-037H) to be logic 1 on the reception of the A bit being logic one for 4 or more consecutive occasions, and set the RAIV (b7, E1-037H) to be logic 0 on the reception of any A bit being logic zero. AISC: = 0: set the AISD (b5, E1-037H) to logic 1 when it is out of basic frame sync and less than 3 zeros are detected in a 512-bit stream, and set the AISD (b5, E1-037H) to logic 0 when 3 or more zeros are detected in a 512-bit stream. = 1: set the AISD (b5, E1-037H) to logic 1 when it is out of basic frame sync and less than 3 zeros are detected in each of 2 consecutive 512-bit stream, and set the AISD (b5, E1-037H) to logic 0 when 3 or more zeros are detected in each of 2 consecutive 512-bit stream. EXCRCERR: The excessive CRC errors is defined as more than 914 CRC errors in one second. One CRC error is counted when the local calculated CRC-4 is not equal to the received CRC-4. = 0: normal operation. = 1: indicate that there are excessive CRC errors in the received data stream. This bit is cleared to 0 after it is read
152
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Framing Status Interrupt Enable (032H, 0B2H, 132H, 1B2H, 232H, 2B2H, 332H, 3B2H) Bit No. Bit Name Type Default 7 C2NCIWE R/W 0 6 OOFE R/W 0 5 OOSMFE R/W 0 4 OOCMFE R/W 0 3 COFAE R/W 0 2 FERE R/W 0 1 SMFERE R/W 1 0 CMFERE R/W 0
C2NCIWE: = 0: disable the interrupt on the INT pin when the C2NCIWI (b7, E1-034H) is logic one. = 1: enable the interrupt on the INT pin when the C2NCIWI is logic one. OOFE: = 0: disable the interrupt on the INT pin when the OOFI (b6, E1-034H) is logic one. = 1: enable the interrupt on the INT pin when the OOFI is logic one. OOSMFE: = 0: disable the interrupt on the INT pin when the OOSMFI (b5, E1-034H) is logic one. = 1: enable the interrupt on the INT pin when the OOSMFI is logic one. OOCMFE: = 0: disable the interrupt on the INT pin when the OOCMFI (b4, E1-034H) is logic one. = 1: enable the interrupt on the INT pin when the OOCMFI is logic one. COFAE: = 0: disable the interrupt on the INT pin when the position of the basic frame alignment signal changes. = 1: enable the interrupt on the INT pin when the position of the basic frame alignment signal changes. FERE: = 0: disable the interrupt on the INT pin when there is error in the basic frame alignment pattern. = 1: enable the interrupt on the INT pin when there is error in the basic frame alignment pattern. SMFERE: = 0: disable the interrupt on the INT pin when there is an error in the signaling multi-frame alignment pattern. = 1: enable the interrupt on the INT pin when there is an error in the signaling multi-frame alignment pattern. CMFERE: = 0: disable the interrupt on the INT pin when there is error in the CRC multi-frame alignment pattern. = 1: enable the interrupt on the INT pin when there is error in the CRC multi-frame alignment pattern.
153
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Maintenance / Alarm Status Interrupt Enable (033H, 0B3H, 133H, 1B3H, 233H, 2B3H, 333H, 3B3H) Bit No. Bit Name Type Default 7 RAIE R/W 0 6 RMAIE R/W 0 5 AISDE R/W 0 4 Reserved 3 REDE R/W 0 2 AISE R/W 0 1 FEBEE R/W 0 0 CRCEE R/W 0
RAIE: = 0: disable the interrupt on the INT pin when the RAII (b7, E1-035H) is logic one. = 1: enable the interrupt on the INT pin when the RAII is logic one. RMAIE: = 0: disable the interrupt on the INT pin when the RMAII (b6, E1-035H) is logic one. = 1: enable the interrupt on the INT pin when the RMAII is logic one. AISDE: = 0: disable the interrupt on the INT pin when the AISDI (b5, E1-035H) is logic one. = 1: enable the interrupt on the INT pin when the AISDI is logic one. REDE: = 0: disable the interrupt on the INT pin when the REDI (b3, E1-035H) is logic one. = 1: enable the interrupt on the INT pin when the REDI is logic one. AISE: = 0: disable the interrupt on the INT pin when the AISI (b2, E1-035H) is logic one. = 1: enable the interrupt on the INT pin when the AISI is logic one. FEBEE: = 0: disable the interrupt on the INT pin when a logic 0 is received in the E1 (the first bit in TS0 in the 13th Frame of CRC-4 Multi-Frame) or E2 (the first bit in TS0 in the 15th Frame of CRC-4 Multi-Frame) bit. = 1: enable the interrupt on the INT pin when a logic 0 is received in the E1 or E2 bit. CRCEE: = 0: disable the interrupt on the INT pin when there is difference between the calculated CRC-4 remainder and the received CRC-4. = 1: enable the interrupt on the INT pin when there is difference between the calculated CRC-4 remainder and the received CRC-4.
154
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Framing Status Interrupt Indication (034H, 0B4H, 134H, 1B4H, 234H, 2B4H, 334H, 3B4H) Bit No. Bit Name Type Default 7 C2NCIWI R X 6 OOFI R X 5 OOSMFI R X 4 OOCMFI R X 3 COFAI R X 2 FERI R X 1 SMFERI R X 0 CMFERI R X
All the bits in this register are clear to 0 after the register is read. C2NCIWI: = 0: no status change on the C2NCIWV (b7, E1-036H). = 1: there is a transition (from 0 to 1 or from 1 to 0) on the C2NCIWV (b7, E1-036H). OOFI: = 0: no status change on the OOFV (b6, E1-036H) = 1: there is a transition (from 0 to 1 or from 1 to 0) on the OOFV (b6, E1-036H). OOSMFI: = 0: no status change on the OOSMFV (b5, E1-036H) = 1: there is a transition (from 0 to 1 or from 1 to 0) on the OOSMFV (b5, E1-036H). OOCMFI: = 0: no status change on the OOCMFV (b4, E1-036H) = 1: there is a transition (from 0 to 1 or from 1 to 0) on the OOCMFV (b4, E1-036H). COFAI: = 0: the position of the basic frame alignment signal does not change = 1: the position of the basic frame alignment signal changes. FERI: = 0: there is no error in the basic frame alignment pattern. = 1: there is an error in the basic frame alignment pattern. SMFERI: = 0: there is no error in the signaling multi-frame alignment pattern. = 1: there is an error in the signaling multi-frame alignment pattern. CMFERI: = 0: there is no error in the CRC multi-frame alignment pattern. = 1: there is an error in the CRC multi-frame alignment pattern.
155
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Maintenance / Alarm Status Interrupt Indication (035H, 0B5H, 135H, 1B5H, 235H, 2B5H, 335H, 3B5H) Bit No. Bit Name Type Default 7 RAII R X 6 RMAII R X 5 AISDI R X 4 Reserved 3 REDI R X 2 AISI R X 1 FEBEI R X 0 CRCEI R X
All the bits in this register are clear to 0 after the register is read. RAII: = 0: no status change on the RAIV (b7, E1-037H). = 1: there is a transition (from 0 to 1 or from 1 to 0) on the RAIV (b7, E1-037H). RMAII: = 0: no status change on the RMAIV (b6, E1-037H). = 1: there is a transition from 0 to 1 or from 1 to 0 on the RMAIV (b6, E1-037H). AISDI: = 0: no status change on the AISD (b5, E1-037H). = 1: there is a transition from 0 to 1 or from 1 to 0 on the AISD (b5, E1-037H). REDI: = 0: no status change on the RED (b3, E1-037H). = 1: there is a transition from 0 to 1 or from 1 to 0 on the RED (b3, E1-037H). AISI: = 0: no status change on the AIS (b2, E1-037H). = 1: there is a transition from 0 to 1 or from 1 to 0 on the AIS (b2, E1-037H). FEBEI: = 0: No logic 0 is received in the E1 or E2 bit. = 1: A logic 0 is received in the E1 or E2 bit. CRCEI: = 0: No difference between the calculated CRC-4 remainder and the received CRC-4. = 1: There is difference between the calculated CRC-4 remainder and the received CRC-4 remainder.
156
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Framing Status (036H, 0B6H, 136H, 1B6H, 236H, 2B6H, 336H, 3B6H) Bit No. Bit Name Type Default 7 C2NCIWV R X 6 OOFV R X 5 OOSMFV R X 4 OOCMFV R X 3 OOOFV R X 2 RAICCRCV R X 1 CFEBEV R X 0 V52LINKV R X
C2NCIWV: = 0: the Frame Processor does not operate in CRC to non-CRC inter-working mode. = 1: the Frame Processor operates in CRC to non-CRC inter-working mode. OOFV: = 0: the Basic Frame is in sync. = 1: the Basic Frame is out of sync. OOSMFV: = 0: the Signaling Multi-Frame is in sync. = 1: the Signaling Multi-Frame is out of sync. OOCMFV: = 0: the CRC Multi-Frame is in sync. = 1: the CRC Multi-Frame is out of sync OOOFV: = 0: the offline frame is in sync. = 1: the offline frame is out of sync. RAICCRCV: = 0: normal operation. = 1: the remote alarm (logic 1 in A bit) and the FEBE (logic 0 in bit E1 or E2) have existed for a period of 10ms. CFEBEV: = 0: normal operation. = 1: FEBE (logic 0 in bit E1 and E2) has existed for more than or equal to 990 occasions in each second for 5 consecutive seconds. V52LINKV: = 0: V5.2 link ID signal is not received. = 1: V5.2 link ID signal is received, i.e., 2 out of 3 Sa7 bits are logic zeros
157
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Maintenance / Alarm Status (037H, 0B7H, 137H, 1B7H, 237H, 2B7H, 337H, 3B7H) Bit No. Bit Name Type Default 7 RAIV R X 6 RMAIV R X 5 AISD R X 4 Reserved 3 RED R X 2 AIS R X 1 Reserved 0
RAIV: This bit indicates the value of the Remote Alarm Indication (A) bit. = 0: the A bit is logic 0. = 1: RAI is detected according to the criterion set in the RAIC (b3, E1-031H). When the RAIC is 0, RAI is detected when the A bit is received as logic 1. When the RAIC is 1, RAI is detected when the A bit is received as logic 1 for 4 or more consecutive occasions. The RAIV is updated every two frames. RMAIV: This bit indicates the value of the Remote Signaling Multi-Frame Alarm Indication (Y) bit. = 0: the Y bit is logic 0. = 1: logic 1 has been received in Y bit for 3 consecutive signaling multi-frames. The RMAIV is updated every 16 frames. AISD: This bit indicates the Alarm Indication Signal (AIS) detect value. The detection of AIS is disabled in unframed mode. = 0: AIS is clear according to the criterion set in the AISC (b1, E1-031H). When the AISC is 0, AIS is clear when 3 or more zeros are detected in a 512-bit stream. When the AISC is 1, AIS is clear when 3 or more zeros are detected in each of 2 consecutive 512-bit stream. = 1: AIS is detected according to the criterion set in the AISC (b1, E1-031H). When the AISC is 0, AIS is detected when it is out of basic frame sync and less than 3 zeros are detected in a 512-bit stream. When the AISC is 1, AIS is detected when it is out of basic frame sync and less than 3 zeros are detected in each of 2 consecutive 512-bit stream. The AISD bit is updated once every 512 bit periods. RED: = 0: out of basic frame sync has been absent for 100ms. = 1: out of basic frame sync has persisted for 100ms. AIS: = 0: the condition of AIS has been absent for 100ms. = 1: the condition of AIS has persisted for 100ms.
158
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Timeslot0 International / National Bits (038H, 0B8H, 138H, 1B8H, 238H, 2B8H, 338H, 3B8H) Bit No. Bit Name Type Default 7 Si[1] R X 6 Si[0] R X 5 A R X 4 Sa[4] R X 3 Sa[5] R X 2 Sa[6] R X 1 Sa[7] R X 0 Sa[8] R X
The content in this register reflects the international bits, Remote Alarm Indication bit and national bits. The Si[1:0] bits are the international bits. The A bit is the Remote Alarm Indication bit. The Sa[4:8] bits are the national bits. Their position is shown in the following table: Frame the Eight Bits in TS0 Type 0 1 2 3 4 5 6 7 FAS Si[1] 0 0 1 1 0 1 1 NFAS Si[0] 1 A Sa[4] Sa[5] Sa[6] Sa[7] Sa[8] Note that the contents of this register are not updated while the the received data stream is out of Basic Frame. Si[1]: Directly reflect the content in the International bit in the latest received FAS frame and is updated on the generation of the IFPI interrupt on FAS frames. Si[0]: Directly reflect the content in the International bit in the latest received NFAS frame and is updated on the generation of the IFPI interrupt on NFAS frames. A: Directly reflect the content in the Remote Alarm Indication (A) bit in the latest received NFAS frame and is updated on the generation of the IFPI interrupt on NFAS frames. Sa[4:8]: Directly reflect the content in the National bit in the latest received NFAS frame and is updated on the generation of the IFPI interrupt on NFAS frames. E1 FRMP CRC Error Counter-LSB (039H, 0B9H, 139H, 1B9H, 239H, 2B9H, 339H, 3B9H) Bit No. Bit Name Type Default 7 CRCERR[7] R X 6 CRCERR[6] R X 5 CRCERR[5] R X 4 CRCERR[4] R X 3 CRCERR[3] R X 2 CRCERR[2] R X 1 CRCERR[1] R X 0 CRCERR[0] R X
The CRCERR[7:0], together with the CRCERR[9:8], represent the number of the CRC errors and update every second. The CRCERR[0] is the LSB.
159
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP CRC Error Counter-MSB / Timeslot16 Extra Bits (03AH, 0BAH, 13AH, 1BAH, 23AH, 2BAH, 33AH, 3BAH) Bit No. Bit Name Type Default 7 OVR R 0 6 NEWDATA R 0 5 X[0] R X 4 Y R X 3 X[1] R X 2 X[2] R X 1 CRCERR[9] R X 0 CRCERR[8] R X
OVR: The overwritten means that the data is still written into the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) without the data being read in the latest one second interval. = 0: the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) are not overwritten. = 1: the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) are overwritten. This bit is clear to 0 after it is read. NEWDATA: = 0: the value in the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) has not been updated with new value. = 1: the value in the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) has been updated with new value. This bit is clear to 0 after it is read. This bit can be polled to determine the 1 second timing boundary used by the Frame Processor. X[0:2], Y: Directly reflect the content in the Extra bits (X[0:2]) and the Remote Signaling Multi-frame Alarm bit (Y) in Frame0 of TS16 of the latest received Signaling Multi-Frame. They are updated on the generation of the IFPI interrupt on NFAS frames. Note that these bits are not updated when the received data stream is out of Basic Frame. The position of the X[2:0] and Y bit is shown in the following table: the Eight Bits in TS16 Frame 0 0 1 2 3 4 5 6 7 0 0 0 0 X[0] Y X[1] X[2] CRCERR[9:8]: The CRCERR[9:8], together with the CRCERR[7:0], represent the number of the CRC errors and update every second. The CRCERR[9] is the MSB.
160
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP National Bit Codeword Interrupt Enables (03BH, 0BBH, 13BH, 1BBH, 23BH, 2BBH, 33BH, 3BBH) Bit No. Bit Name Type Default 7 SaSEL[2] R/W 0 6 SaSEL[1] R/W 0 5 SaSEL[0] R/W 0 4 Sa4E R/W 0 3 Sa5E R/W 0 2 Sa6E R/W 0 1 Sa7E R/W 0 0 Sa8E R/W 0
SaSEL[2:0]: The SaSEL[2:0] select the National Bit Codeword (SaX) to appear in the SaX[1:4] (b3~0, E1-03DH) of the National Bit Codeword register. SaSEL[2:0] National Bit Codeword 001 010 Reserved 011 100 Sa4 101 Sa5 110 Sa6 111 Sa7 000 Sa8 Sa4E, Sa5E, Sa6E, Sa7E, Sa8E: = 0 (in any of the 5 bits): disable the interrupt on the INT pin when the value is changed in its corresponding SaX[1:4] (b3~0, E1-03DH). = 1 (in any of the 5 bits): enable the interrupt on the INT pin when the value is changed in its corresponding SaX[1:4] (b3~0, E1-03DH) (X is 4 through 8). The interrupt enable should be logic 0 for any bit receiving a HDLC data link. E1 FRMP National Bit Codeword Interrupts (03CH, 0BCH, 13CH, 1BCH, 23CH, 2BCH, 33CH, 3BCH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 Sa4I R X 3 Sa5I R X 2 Sa6I R X 1 Sa7I R X 0 Sa8I R X
Sa4I, Sa5I, Sa6I, Sa7I, Sa8I: = 0 (in any of the 5 bits): the value is not changed in its corresponding SaX[1:4] (b3~0, E1-03DH) bits (X is 4 through 8). = 1 (in any of the 5 bits): the value is changed in its corresponding SaX[1:4] (b3~0, E1-03DH) bits (X is 4 through 8). This bit is clear to 0 after the register is read.
161
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP National Bit Codeword (03DH, 0BDH, 13DH, 1BDH, 23DH, 2BDH, 33DH, 3BDH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 SaX[1] R X 2 SaX[2] R X 1 SaX[3] R X 0 SaX[4] R X
These bits directly reflect the content in the SaX nibble codeword of the CRC Sub Multi-Frame. "X" is determined by the SaSEL[2:0] (b7~5, E103BH). SaX[1] is the first SaX bit of the Sub Multi-Frame and analogically. The SaX[1:4] are debounced. They are updated only when two consecutive codewords are the same. E1 FRMP Frame Pulse/Alarm/V5.2 Link ID Interrupt Enables (03EH, 0BEH, 13EH, 1BEH, 23EH, 2BEH, 33EH, 3BEH) Bit No. Bit Name Type Default 7 OOOFE R/W 0 6 RAICCRCE R/W 0 5 CFEBEE R/W 0 4 V52LINKE R/W 0 3 IFPE R/W 0 2 ICSMFPE R/W 0 1 ICMFPE R/W 0 0 ISMFPE R/W 0
OOOFE: = 0: disable the interrupt on the INT pin when the OOOFI (b7, E1-03FH) is logic one. = 1: enable the interrupt on the INT pin when the OOOFI (b7, E1-03FH) is logic one. RAICCRCE: = 0: disable the interrupt on the INT pin when the remote alarm (logic 1 in A bit) and the FEBE (logic 0 in bit E1 or E2) being existed for a period of 10ms. = 1: enable the interrupt on the INT pin when the remote alarm (logic 1 in A bit) and the FEBE (logic 0 in bit E1 or E2) being existed for a period of 10ms. CFEBEE: = 0: disable the interrupt on the INT pin when the FEBE (logic 0 in bit E1 or E2) has existed for more than 990 occasions in each second for 5 consecutive seconds. = 1: enable the interrupt on the INT pin when the FEBE (logic 0 in bit E1 or E2) has existed for more than 990 occasions in each second for 5 consecutive seconds. V52LINKE: = 0: disable the interrupt on the INT pin when the V52LINKI is logic one. = 1: enable the interrupt on the INT pin when the V52LINKI (b4, E1-03FH) is logic one. IFPE: = 0: disable the interrupt on the INT pin when the first bit of each basic frame is received. = 1: enable the interrupt on the INT pin when the first bit of each basic frame is received. ICSMFPE: = 0: disable the interrupt on the INT pin when the first bit of each CRC sub-multi-frame is received. = 1: enable the interrupt on the INT pin when the first bit of each CRC sub-multi-frame is received. ICMFPE: = 0: disable the interrupt on the INT pin when the first bit of each CRC multi-frame is received. = 1: enable the interrupt on the INT pin when the first bit of each CRC multi-frame is received. ISMFPE: = 0: disable the interrupt on the INT pin when the first bit of each signaling multi-frame is received. = 1: enable the interrupt on the INT pin when the first bit of each signaling multi-frame is received.
162
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMP Frame Pulse / Alarm Interrupts (03FH, 0BFH, 13FH, 1BFH, 23FH, 2BFH, 33FH, 3BFH) Bit No. Bit Name Type Default 7 OOOFI R X 6 RAICCRCI R X 5 CFEBEI R X 4 V52LINKI R X 3 IFPI R X 2 ICSMFPI R X 1 ICMFPI R X 0 ISMFPI R X
The bits of this register are clear to 0 after the register is read. OOOFI: = 0: there is no transition (from 0 to 1 or from I to 0) on the OOOFV (b3, E1-036H). = 1: there is a transition (from 0 to 1 or from I to 0) on the OOOFV (b3, E1-036H). RAICCRCI: = 0: there is no transition from normal operation to the remote alarm (logic 1 in A bit) or the FEBE (logic 0 in bit E1 or E2) has being absent for a period of 10ms. = 1: there is a transition from normal operation to the remote alarm (logic 1 in A bit) and the FEBE (logic 0 in bit E1 or E2) has being existed for a period of 10ms. CFEBEI: = 0: there is no transition from normal operation to FEBE (logic 0 in bit E1 or E2) existed for more than 990 occasions in each second for 5 consecutive seconds. = 1: there is a transition from normal operation to FEBE (logic 0 in bit E1 or E2) existed for more than 990 occasions in each second for 5 consecutive seconds. V52LINKI: = 0: there is no transition (from 0 to 1 or from 1 to 0) on the V52LINKV (b0, E1-036H). = 1: there is a transition (from 0 to 1 or from 1 to 0) on the V52LINKV (b0, E1-036H). IFPI: = 0: the received bit is not the first bit of each Basic Frame. = 1: the first bit of each Basic Frame is received. ICSMFPI: = 0: the received bit is not the first bit of each CRC sub-Multi-Frame. = 1: the first bit of each CRC sub-Multi-Frame is received. ICMFPI: = 0: the received bit is not the first bit of each CRC multi-frame. = 1: the first bit of each CRC multi-frame is received. ISMFPI: = 0: the received bit is not the first bit of each Signaling Multi-Frame. = 1: the first bit of each Signaling Multi-Frame is received.
163
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMG Configuration (040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H) Bit No. Bit Name Type Default 7 FRESH R/W 0 6 SIGEN R/W 1 5 DLEN R/W 1 4 GENCRC R/W 0 3 FDIS R/W 0 2 FEBEDIS R/W 0 1 INDIS R/W 0 0 XDIS R/W 0
FRESH: = 0: normal operation. = 1: initiate the FIFO in the Frame Generator block. After initialization of the backplane interface, the user should write 1 into this bit and then clear it. SIGEN, DLEN: These two bits select the signaling sources for TS16. They are valid when the AIS (b0, E1-041H) is logic 0: SIGEN, DLEN Signaling Source 00 Signaling insertion disabled or CCS enabled. TS16 data is taken directly from the input TSDn TS16 or from the THDLC if the THDLC selects this inserted position. The XDIS (b0, E1-040H) must also be set to logic 1 to disable the insertion of the extra bits in TS16 of frame 0. 01 Reserved 01 Reserved 11 CAS enabled. TS16 data is taken from either TSSIGn stream or from the TPLC Signaling/PCM Control byte as selected on a per-timeslot basis via the SIGSRC (b4, E1-TPLC-indirect registers - 61~7FH). However, the TS16 of Frame0 of Signaling MultiFrame is overwritten by `0000X[0]YX[1]X[2]'. GENCRC: = 0: CRC Multi-Frame generation is disabled. Then the International Bits are replaced with the value contained in the Si[1:0] (b7~6, E1-042H) if the INDIS (b1, E1-040H) is enabled (logic 0), or, if the INDIS (b1, E1-040H) is not enabled, the international bits are taken directly from TSDn/MTSD. = 1: CRC Multi-Frame generation is enabled. When CRC Multi-Frame is generated, the international bits on the TSDn pin are replaced with CRC Multi-Frame alignment pattern and calculated CRC-4 bits. The CRC bits calculated during the transmission of the SMFn are transmitted in the following SMF (SMF n+1). If the FEBEDIS (b2, E1-040H) is enabled (logic 0), the FEBE indication is inserted in the E1 and E2 bit positions. The setting to 1 is valid when the FDIS (b3, E1-040H) and the INDIS (b1, E1-040H) are logic 0. FDIS: = 0: replace the data on the TS0 of FAS on the TSDn/MTSD pin with Basic Frame alignment sequence (FAS). = 1: keep the data on the TSDn/MTSD pin to pass through the Frame Generation transparently. The values in the control bits GENCRC (b4, E1040H), FEBEDIS (b2, E1-040H) and INDIS (b1, E1-040H) are ignored. FEBEDIS: Valid when the FDIS (b3, E1-040H) and the INDIS (b1, E1-040H) are logic 0 and the GENCRC (b4, E1-040H) is logic 1. = 0: the international bit of frame 13 & 15 are for FEBE indication. = 1: FEBE indication is disabled. INDIS: = 0: enabled to replace the international bit. = 1: disable to replace the international bit. The value of the international bit is directly taken from the TSDn/MTSD or from the THDLC if the THDLC selects this inserted position. XDIS: Valid when FDIS (b3, E1-040H) is logic 0, and the SIGEN (b6, E1-040H) and the DLEN (b5, E1-040H) are logic 1. = 0: replace the extra bits with the setting in the X[2:0]. = 1: ignore the setting in the X[2:0] bits. The value in the extra bits is taken from the TSDn/MTSD.
164
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMG Transmit Alarm / Diagnostic Control (041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H) Bit No. Bit Name Type Default 7 MTRK R/W 0 6 FPATINV R/W 0 5 SPLRINV R/W 0 4 SPATINV R/W 0 3 REMAIS R/W 0 2 MFAIS R/W 0 1 TS16AIS R/W 0 0 AIS R/W 0
MTRK: Valid when the FDIS (b3, E1-040H) is logic 0 and the PCCE (b0, E1-060H) is 1. = 0: ignore the setting in the IDLE Code Byte register. = 1: replace the data on the TS1~15 & TS17~31 with the IDLE code. And when the SIGEN (b6, E1-040H) is logic 1, replace the data on the TS16 with signaling; when the SIGEN (b6, E1-040H) is logic 0, replace the data on the TS16 with IDLE code. FPATINV: Valid when the FDIS (b3, E1-040H) is logic 0. = 0: disable the inversion of the FAS. = 1: enable the inversion of the FAS (from `0011011' to `1100100'). SPLRINV: Valid when the FDIS (b3, E1-040H) is logic 0. = 0: disable the inversion of the 2nd bit of NFAS. = 1: enable the inversion of the 2nd bit of NFAS (from 1 to 0). SPATINV: Valid when the FDIS (b3, E1-040H) is logic 0 and the SIGEN (b6, E1-040H) & the DLEN (b5, E1-040H) are logic 1. = 0: disable the inversion of the Signaling Multi-Frame alignment signal. = 1: enable the inversion of the Signaling Multi-Frame alignment signal (from `0000' to `1111'). REMAIS: Valid when the FDIS (b3, E1-040H) is logic 0. = 0: normal operation. = 1: force the 3rd bit of NFAS to be logic 1. MFAIS: Valid when the FDIS (b3, E1-040H) is logic 0. = 0: normal operation. = 1: force to transmit the Y bit as logic 1. TS16AIS: Valid when the FDIS (b3, E1-040H) is logic 0 and Signaling Multi-Frame generator is enabled. = 0: normal transmission. = 1: force to transmit all ones in TS16 unconditionally. AIS: = 0: normal transmission. = 1: force to transmit all ones on all timeslots unconditionally.
165
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMG International Bits Control (042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H) Bit No. Bit Name Type Default 7 Si[1] R/W 1 6 Si[0] R/W 1 5 4 3 Reserved 2 1 0
Si[1:0]: Valid when the FDIS (b3, E1-040H) and the INDIS (b1, E1-040H) are logic 0. When CRC Multi-Frame generation is disabled (GENCRC is logic 0), the Si[1] and Si[0] bits can be programmed to any value and will be inserted into the first of each FAS frame and NFAS frame, respectively. When CRC Multi-Frame generation is enabled (GENCRC is logic 1), and FEBE indication is disabled (FEBEDIS is logic 1), the values programmed in the Si[1] and Si[0] bit positions are inserted into the E1 & E2 bit positions respectively. When GENCRC is logic 1 and FEBEDIS is logic 0, both Si[1] and Si[0] are ignored. E1 FRMG Extra Bits Control (043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 X[0] R/W 1 2 Reserved 1 X[1] R/W 1 0 X[2] R/W 1
X[2:0]: Valid when the FDIS (b3, E1-040H), the XDIS (b0, E1-040H), the SIGEN (b6, E1-040H) and the DLEN (b5, E1-040H) are all logic 0. Replace the extra bits located in bits 5, 7 & 8 in TS16 of frame 0 of the Signaling Multi-Frame.
166
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMG Interrupt Enable (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 SIGMFE R/W 0 3 FASE R/W 0 2 MFE R/W 0 1 SMFE R/W 0 0 Reserved (must be 0)
SIGMFE: = 0: disable the interrupt on the INT pin when the SIGMFI (b4, E1-045H) is logic one. = 1: enable the interrupt on the INT pin when the SIGMFI (b4, E1-045H) is logic one. FASE: = 0: disable the interrupt on the INT pin when the FASI (b3, E1-045H) is logic one. = 1: enable the interrupt on the INT pin when the FASI (b3, E1-045H) is logic one. MFE: = 0: disable the interrupt on the INT pin when the MFI (b2, E1-045H) is logic one. = 1: enable the interrupt on the INT pin when the MFI (b2, E1-045H) is logic one. SMFE: = 0: disable the interrupt on the INT pin when the SMFI (b1, E1-045H) is logic one. = 1: enable the interrupt on the INT pin when the SMFI (b1, E1-045H) is logic one.
167
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMG Interrupt Status (045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 SIGMFI R X 3 FASI R X 2 MFI R X 1 SMFI R X 0 Reserved
The bits in this register are clear to 0 after the register is read. SIGMFI: Valid when the Signaling Multi-Frame is generated and coincides with the CRC Multi-Frame. = 0: not at the end of the first frame of a Signaling Multi-Frame. = 1: indicate the end of the first frame of a Signaling Multi-Frame. FASI: Valid when the Basic Frame is generated. = 0: not on the boundary of a FAS frame. = 1: indicate the boundary of a FAS frame. MFI: Valid when the CRC-4 Multi-Frame is generated. = 0: not at the end of the first frame of a CRC-4 Multi-Frame. = 1: indicate the end of the first frame of a CRC-4 Multi-Frame. SMFI: Valid when the CRC-4 Multi-Frame is generated. = 0: not at the end of the first frame of a CRC-4 Sub Multi-Frame. = 1: indicate the end of the first frame of a CRC-4 Sub Multi-Frame.
168
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 FRMG National Bit Codeword Select (046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H) Bit No. Bit Name Type Default 7 SaSEL[2] R/W 0 6 SaSEL[1] R/W 0 5 SaSEL[0] R/W 0 4 3 2 Reserved 1 0
SaSEL[2:0]: The SaSEL[2:0] select which National Bit Codeword (SaX) will be replaced by the SaX[1:4] (b3~0, E1-047H). SaSEL[2:0] National Bit Codeword 000 001 Reserved 010 011 Sa4 100 Sa5 101 Sa6 110 Sa7 111 Sa8 E1 FRMG National Bit Codeword (047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H) Bit No. Bit Name Type Default 7 SaX_EN[1] R/W 0 6 SaX_EN[2] R/W 0 5 SaX_EN[3] R/W 0 4 SaX_EN[4] R/W 0 3 SaX[1] R/W 1 2 SaX[2] R/W 1 1 SaX[3] R/W 1 0 SaX[4] R/W 1
SaX_ENn: Valid when the FDIS (b3, E1-040H) is logic 0, and the INDIS (b1, E1-040H) is logic 0. = 0: disable the corresponding bit in the SaX[1:4] to replace the national bit codeword selected by the SaSEL[2:0]. = 1: enable the corresponding bit in the SaX[1:4] to replace the national bit codeword selected by the SaSEL[2:0]. SaX[1:4]: These bits are the codeword to be inserted into a CRC-4 sub-multiframe. The setting in the SaX[1:4] will replace the national bits which are assigned by the SaSEL[2:0]. If the code word is written during SMF I of a CRC-4 Multi-Frame, it will appear in the SaX[1:4] bits of SMF II of the same Multi-frame. If the code word is written during SMF II of a Multi-Frame, its contents will be latched internally and will appear in SMF I of the next Multi-Frame.
169
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RHDLC #1, #2, #3 Configuration (048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 MEN R/W 0 2 MM R/W 0 1 TR R/W 0 0 EN R/W 0
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, E1-00AH). MEN, MM: The MEN & MM define the address matching mode: MEN MM Address Matching Mode 0 X No address matching is needed. All the HDLC data are stored in the FIFO. 1 0 The HDLC data are stored in the FIFO when the first byte is all ones or the same as the setting in the PA[7:0] (b7~0, E1-04CH) or the SA[7:0] (b7~0, E1-04DH). 1 1 The HDLC data are stored in the FIFO when the most significant 6 bits in the first byte are all ones or the same as the setting in the PA[7:2] (b7~2, E1-04CH)or the SA[7:2] (b7~2, E1-04DH). TR: = 0: Normal operation. = 1: force the RHDLC to immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts and initiate a new HDLC search. This bit is clear to 0 after a rising and falling edge occur on the internal clock or after the register is read. EN: = 0: disable the operation of the RHDLC block and all the FIFO buffer and interrupts are cleared. = 1: enable the operation of the RHDLC block and the HDLC opening flag will be searched immediately. If the EN is set from logic 1 to logic 0 and back to logic 1, the RHDLC will immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts and initiate a new HDLC search.
170
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RHDLC #1, #2, #3 Interrupt Control (049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H) Bit No. Bit Name Type Default 7 INTE R/W 0 6 INTC[6] R/W 0 5 INTC[5] R/W 0 4 INTC[4] R/W 0 3 INTC[3] R/W 0 2 INTC[2] R/W 0 1 INTC[1] R/W 0 0 INTC[0] R/W 0
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, E1-00AH). INTE: = 0: disable the interrupt on the INT pin when there is a transition from 0 to 1 on the INTR (b0, E1-04AH). = 1: enable the interrupt on the INT pin when there is a transition from 0 to 1 on the INTR (b0, E1-04AH). INTC[6:0]: These bits set the interrupt threshold point of the FIFO buffer. Exceeding the set point will cause an interrupt, and the interrupt will persist until the FIFO is empty. The set point is decimal 128 when the INTC[6:0] is all zeros. The contents of this register should only be changed when the EN (b0, E1-048H) is logic 0. This prevents any erroneous interrupt generation.
171
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RHDLC #1, #2, #3 Status (04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH) Bit No. Bit Name Type Default 7 FE R X 6 OVR R X 5 COLS R X 4 PKIN R X 3 PBS[2] R X 2 PBS[1] R X 1 PBS[0] R X 0 INTR R X
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, E1-00AH). FE: = 0: the FIFO is loaded with data. = 1: the FIFO is empty. OVR: The overwritten condition occurs when data are written over unread data in the FIFO buffer. This bit is cleared to 0 after the register is read. = 0: no overwriting occurs. = 1: the FIFO is overwritten, and then the FIFO is reset , which cause the COLS and PKIN to be reset to logic 0. COLS: This bit reflects the HDLC link status change. = 0: normal operation. = 1: the first HDLC opening flag sequence (7E) activated the HDLC or the HDLC abort sequence (7F) deactivated the HDLC is detected. This bit is cleared to 0 after the bit is read, or after the OVR transits to be logic 1, or after the EN is clear. PKIN: = 0: a HDLC packet has not been written into the FIFO. = 1: a HDLC packet has been written into the FIFO. This bit is cleared to 0 after the bit is read, or after the OVR transitions to logic 1. PBS[2:0]: The PBS[2:0] indicate the status of the last byte read from the FIFO. PBS[2:0] Status of the Data 000 Normal data 001 A dummy byte to indicate the first HDLC opening flag sequence (7E) was detected, which means the HDLC link became active. 010 A dummy byte to indicate the HDLC abort sequence (7F) was detected, which means the HDLC link became inactive. 011 Reserved. 100 The last byte of a non-aborted HDLC packet was received. The HDLC packet is in an integer number of bytes and has no FCS error.. 101 The last byte of a non-aborted HDLC packet was received and a non-integer number of bytes are in the packet. 110 The last byte of a non-aborted HDLC packet was received. The HDLC packet is in an integer number of bytes and has FCS errors. 111 The last byte of a non-aborted HDLC packet was received. The HDLC packet is in a non-integer number of bytes and has FCS errors.. INTR: = 0: no interrupt sources in the HDLC Receiver block occurs = 1: any one of the interrupt sources in the HDLC Receiver block occurs. The interrupt sources in the HDLC Receiver are: 1. Receiving the first 7E opening flag sequence which activates the HDLC link; 2. A packet was received; 3. Change of link status; 4. Exceeding the set point of the FIFO which is defined in the INTC[6:0] (b6~0, E1-049H); 5. Over-writting the FIFO. This bit is cleared to 0 after the bit is read.
172
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RHDLC #1, #2, #3 Data (04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH) Bit No. Bit Name Type Default 7 RD[7] R X 6 RD[6] R X 5 RD[5] R X 4 RD[4] R X 3 RD[3] R X 2 RD[2] R X 1 RD[1] R X 0 RD[0] R X
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, E1-00AH). RD[7:0]: This register represents the bytes read from the FIFO. This register should not be accessed at a rate greater than 1/15 of the XCK rate. The RD[0] corresponds to the first bit of the serial received data from the FIFO. E1 RHDLC #1, #2, #3 Primary Address Match (04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH) Bit No. Bit Name Type Default 7 PA[7] R/W 1 6 PA[6] R/W 1 5 PA[5] R/W 1 4 PA[4] R/W 1 3 PA[3] R/W 1 2 PA[2] R/W 1 1 PA[1] R/W 1 0 PA[0] R/W 1
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, E1-00AH). PA[7:0]: These bits stipulate the primary address pattern. PA[0] stores the first bit of the serial data. E1 RHDLC #1, #2, #3 Secondary Address Match (04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH) Bit No. Bit Name Type Default 7 SA[7] R/W 1 6 SA[6] R/W 1 5 SA[5] R/W 1 4 SA[4] R/W 1 3 SA[3] R/W 1 2 SA[2] R/W 1 1 SA[1] R/W 1 0 SA[0] R/W 1
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, E1-00AH). SA[7:0]: These bits stipulate the secondary address pattern. SA[0] stores the first bit of the serial data.
173
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC #1, #2, #3 Configuration (050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H) Bit No. Bit Name Type Default 7 FLGSHARE R/W 1 6 FIFOCLR R/W 0 5 Reserved 4 3 EOM R/W 0 2 ABT R/W 0 1 CRC R/W 1 0 EN R/W 0
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, E1-00AH). FLGSHARE: = 0: the opening flag of the next HDLC frame and closing flag of the current HDLC frame are separate. = 1: the opening flag of the next HDLC frame and closing flag of the current HDLC frame are shared FIFOCLR: = 0: normal operation. = 1: clear the FIFO. EOM: = 0: normal operation. = 1: a positive transition of this bit starts a packet transmission. Then if the CRC(b1, E1-050H) is set, the 16-bit FCS word is appended to the last data byte transmitted. ABT: = 0: normal operation. = 1: transmit the 7F abort sequence after the current setting in the Transmit Data register is transmitted, so that the FIFO is cleared and all data in the FIFO will be lost. Aborts are continuously sent and the FIFO is held in reset until this bit is reset to a logic 0. At least one Abort sequence will be sent when the ABT transitions from logic 0 to logic 1. CRC: = 0: do not append the CRC-16 frame check sequences (FCS) to the end of the HDLC data. = 1: append the FCS to the end of the HDLC data. EN: = 0: disable the operation of the THDLC block. = 1: enable the operation of the THDLC block and flag sequences are sent until data is written into the THDLC Transmit Data register and the EOM is set to logic 1.
174
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC #1, #2, #3 Upper Transmit Threshold (051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H) Bit No. Bit Name Type Default 7 Reserved 6 UTHR[6] R/W 1 5 UTHR[5] R/W 0 4 UTHR[4] R/W 0 3 UTHR[3] R/W 0 2 UTHR[2] R/W 0 1 UTHR[1] R/W 0 0 UTHR[0] R/W 0
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, E1-00AH). UTHR[6:0]: These bits define the upper fill level of the FIFO. Once the fill level exceeds the UTHR[6:0] value, the data stored in the FIFO will start to transmit. The transmission will not stop until the complete packet is transmitted and the THDLC FIFO fill level is below UTHR[6:0] + 1. It should be greater than the value of the LINT[6:0] unless both are equal to 00H. E1 THDLC #1, #2, #3 Lower Interrupt Threshold (052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H) Bit No. Bit Name Type Default 7 Reserved 6 LINT[6] R/W 0 5 LINT[5] R/W 0 4 LINT[4] R/W 0 3 LINT[3] R/W 0 2 LINT[2] R/W 1 1 LINT[1] R/W 1 0 LINT[0] R/W 1
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, E1-00AH). LINT[6:0]: These bits define the fill level of the FIFO that can cause an interrupt. That is, when the fill level of the FIFO is below the LINT[6:0], an interrupt will be generated. The LINT[6:0] should be less than the value of the UTHR[6:0] unless both are equal to 00H.
175
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC #1, #2, #3 Interrupt Enable (053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 FULLE R/W 0 2 OVRE R/W 0 1 UDRE R/W 0 0 LFILLE R/W 0
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, E1-00AH). FULLE: = 0: disable the interrupt on the INT pin when the FULLI (b3, E1-054H) is logic 1. = 1: enable the interrupt on the INT pin when the FULLI (b3, E1-054H) is logic 1. OVRE: = 0: disable the interrupt on the INT pin when the OVRI (b2, E1-054H) is logic 1. = 1: enable the interrupt on the INT pin when the OVRI (b2, E1-054H) is logic 1. UDRE: = 0: disable the interrupt on the INT pin when the UDRI (b1, E1-054H) is logic 1. = 1: enable the interrupt on the INT pin when the UDRI (b1, E1-054H) is logic 1. LFILLE: = 0: disable the interrupt on the INT pin when the LFILLI (b0, E1-054H) is logic 1. = 1: enable the interrupt on the INT pin when the LFILLI (b0, E1-054H) is logic 1.
176
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC #1, #2, #3 Interrupt Status / UDR Clear (054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H) Bit No. Bit Name Type Default 7 Reserved 6 FULL R X 5 BLFILL R X 4 Reserved 3 FULLI R X 2 OVRI R X 1 UDRI R X 0 LFILLI R X
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, E1-00AH). FULL: = 0: the THDLC FIFO is not full. = 1: the THDLC FIFO is full (128 bytes). BLFILL: = 0: the fill level in the THDLC FIFO is not below the value of the LINT[6:0] (b6~0, E1-052H). = 1: the fill level in the THDLC FIFO is empty or below the value of the LINT[6:0] (b6~0, E1-052H). FULLI: = 0: there is no transition (from 0 to 1) on the FULL. = 1: there is a transition (from 0 to 1) on the FULL. This bit is cleared to 0 after the bit is read. OVRI: The Over-Written is that the THDLC FIFO was already full when another data byte was written to the THDLC Transmit Data register. = 0: the THDLC FIFO is not overwritten. = 1: the THDLC FIFO is overwritten. This bit is cleared to 0 after the bit is read. UDRI: The Under-Run is that the THDLC was in the process of transmitting a packet when it ran out of data to be transmitted. = 0: the THDLC FIFO is not under-run. = 1: the THDLC FIFO is under-run. This bit is cleared to 0 after the bit is read. LFILLI: = 0: there is no transition (from 0 to 1) on the BLFILL. = 1: there is a transition (from 0 to 1) on the BLFILL. This bit is cleared to 0 after the bit is read.
177
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 THDLC #1, #2, #3 Transmit Data (055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H) Bit No. Bit Name Type Default 7 TD[7] R/W X 6 TD[6] R/W X 5 TD[5] R/W X 4 TD[4] R/W X 3 TD[3] R/W X 2 TD[2] R/W X 1 TD[1] R/W X 0 TD[0] R/W X
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, E1-00AH). The content is the data to be transmitted. It is serially transmitted (TD[0] is the first). E1 ELSB Interrupt Enable / Status (059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 SLIPE R/W 0 1 SLIPD R X 0 SLIPI R X
SLIPE: = 0: disable the interrupt on the INT pin when a slip occurs. = 1: enable the interrupt on the INT pin when a slip occurs. SLIPD: This bit makes sense only when the SLIPI is logic 1. = 0: the latest slip is due to the Elastic Store Buffer being empty; a frame was duplicated. = 1: the latest slip is due to the Elastic Store Buffer being full; a frame was deleted. SLIPI: = 0: no slip occurs. = 1: a slip occurs. This bit is cleared to 0 after the bit is read. E1 ELSB Idle Code (05AH, 0DAH, 15AH, 1DAH, 25AH, 2DAH, 35AH, 3DAH) Bit No. Bit Name Type Default 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1
These bits set the idle code that will replace the data on the RSDn/MRSD when it is out of Basic Frame and the TRKEN (b1, E1-001H) is logic 1. D7 is the first bit to be inserted. The writing of the idle code pattern is asynchronous with respect to the output data clock. One timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame.
178
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RPLC Configuration (05CH, 0DCH, 15CH, 1DCH, 25CH, 2DCH, 35CH, 3DCH) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 PCCE R/W 0
PCCE: = 0: the per-TS functions in RPLC are disabled. = 1: the per-TS functions in RPLC are enabled. E1 RPLC P Access Status (05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH) Bit No. Bit Name Type Default 7 BUSY R 0 6 5 4 3 Reserved 2 1 0
BUSY: = 0: no reading or writing operation on the indirect registers. = 1: an internal indirect register is being accessed, any new operation on the internal indirect register is not allowed. This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 490ns. No operations to the indirect registers are possible until this bit is logic 0.
179
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RPLC Channel Indirect Address / Control (05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH) Bit No. Bit Name Type Default 7 R/WB R/W 0 6 A6 R/W 0 5 A5 R/W 0 4 A4 R/W 0 3 A3 R/W 0 2 A2 R/W 0 1 A1 R/W 0 0 A0 R/W 0
Writing to this register with a valid address and R/WB bit initiates an internal operation cycle to the indirect registers. R/WB: = 0: write the data to the specified indirect register. = 1: read the data from the specified indirect register. A[6:0]: Specify the address of the indirect registers (from 20H to 7FH) for the microprocessor access. E1 RPLC Channel Indirect Data Buffer (05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH) Bit No. Bit Name Type Default 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
This register hold the value which will be read from or write into the indirect registers (from 20H to 7FH). If data is to be written to the indirect registers, the byte to be written must be written into this register before the target indirect register's address and R/WB=0 is written into the Address/ Control register, initiating the access. If data is to be read from the indirect registers, only the target indirect register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 490 ns, this register will contain the requested data byte. RPLC Indirect Registers Map Per-TS Configuration Byte for TS0 ~ TS31 Data Trunk Conditioning Code Byte for TS0 ~ TS31 Signaling Trunk Conditioning Byte for TS1 ~ TS31
20H ~3FH 40H ~5FH 61H ~ 7FH
180
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RPLC Per-TS Configuration Registers (RPLC Indirect Registers 20H - 3FH) Bit No. Bit Name Type Default 7 TEST R/W X 6 DTRKC/NxTS R/W X 5 STRKC R/W X 4 DMW R/W X 3 DMWALAW R/W X 2 SIGNINV R/W X 1 RINV[1] R/W X 0 RINV[0] R/W X
TEST: = 0: disable the data in the corresponding timeslot to be tested by PRGD. = 1: enable the data in the corresponding timeslot to be extracted to PRGD for test (when the RXPATGEN [b2, E1-00CH] is logic 0), or enable the test pattern from PRGD to replace the data in the corresponding timeslot for test (when the RXPATGEN [b2, E1-00CH] is logic 1). All the timeslots that are extracted to the PRGD are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all timeslots set to be replaced with PRGD test pattern data are concatenated replaced by the PRBS. DTRKC/NxTS: = 0: disable the data in the corresponding timeslot to be replaced by the data set in the DTRK[7:0] (b7~0, E1-RPLC-indirect registers-40~5FH) when output on the RSDn/MRSD pin. = 1: enable the data in the corresponding timeslot to be replaced by the data set in the DTRK[7:0] (b7~0, E1-RPLC-indirect registers-40~5FH) when output on the RSDn/MRSD pin. In addition, it controls the RSCKn of the corresponding timeslot in Receive Clock Slave Fractional E1 mode: = 0: RSCKn is clocked for the corresponding timeslot. = 1: RSCKn is held in its inactive state. STRKC: = 0: disable the signaling of the corresponding timeslot to be replaced by the data set in the A, B, C, D (b3~0, E1-RPLC-indirect registers61~7FH) when output on the RSSIGn/MRSSIG pin. = 1: enable the signaling of the corresponding timeslot to be replaced by the data set in the A, B, C, D (b3~0, E1-RPLC-indirect registers61~7FH) when output on the RSSIGn/MRSSIG pin. DMW: = 0: disallow the data in the corresponding timeslot to be replaced by a digital milliwatt pattern when output on the RSDn/MRSD pin. = 1: enable the data in the corresponding timeslot to be replaced by a digital milliwatt pattern when output on the RSDn/MRSD pin. DMWALAW: = 0: the milliwatt pattern is the -Law pattern. = 1: the milliwatt pattern is the A-Law pattern. SIGNINV, RINV[1:0]: The SIGNINV and the RINV[1:0] bits select the bits in the corresponding timeslot to be inverted when output on the RSDn/MRSD pin: SIGNINV RINV[1:0] Bits Inverted 0 00 No inversion 0 01 Invert the even bits (2, 4, 6, 8) of the timeslot (bit 1 is the MSB) 0 10 Invert the odd bits (1, 3, 5, 7) of the timeslot (bit 1 is the MSB) 0 11 Invert all the bits of the timeslot 1 00 Invert the bit 1 (MSB) of the timeslot 1 01 Invert the bits 1, 2, 4, 6 and 8 of the timeslot 1 10 Invert the bits 3, 5 and 7 of the timeslot 1 11 Invert all the bits of the timeslot except the MSB (bit1) The priority of the RPLC operation on the RSDn pin from high to low is: Extract data to PRGD for test; Replace the data with the value in the DTRK[7:0]; Replace the data with the milliwatt pattern; Replace the data with the pattern generated in the PRGD; Invert the bit.
181
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RPLC Data Trunk Conditioning Code Byte Registers (RPLC Indirect Registers 40H - 5FH) Bit No. Bit Name Type Default 7 DTRK7 R/W X 6 DTRK6 R/W X 5 DTRK5 R/W X 4 DTRK4 R/W X 3 DTRK3 R/W X 2 DTRK2 R/W X 1 DTRK1 R/W X 0 DTRK0 R/W X
They contain the data that will replace the data output on the RSDn/MRSD pin when the corresponding bit DTRKC/NxTS (b6, E1-RPLC-indirect registers-20~3FH) is logic 1. The DTRK7 is the MSB. E1 RPLC Signaling Trunk Conditioning Byte Registers (RPLC Indirect Registers 61H - 7FH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 A R/W X 2 B R/W X 1 C R/W X 0 D R/W X
These bits contain the data that will replace the data output on the RSSIGn/MRSSIG pin when the corresponding STRKC (b5, E1-RPLC-indirect registers-20~3FH) is logic 1. They are in the least significant nibble.
182
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 TPLC Configuration (060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 PCCE R/W 0
PCCE: = 0: the per-TS functions in TPLC are disabled. = 1: the per-TS functions in TPLC are enabled. E1 TPLC P Access Status (061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H) Bit No. Bit Name Type Default 7 BUSY R 0 6 5 4 3 Reserved 2 1 0
BUSY: = 0: no reading or writing operation on the indirect registers. = 1: an internal indirect register is being accessed, any new operation on the internal indirect register is not allowed. This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 490ns. No more operations to the indirect registers could be done until this bit is cleared.
183
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 TPLC Channel Indirect Address / Control (062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H) Bit No. Bit Name Type Default 7 R/WB R/W 0 6 A6 R/W 0 5 A5 R/W 0 4 A4 R/W 0 3 A3 R/W 0 2 A2 R/W 0 1 A1 R/W 0 0 A0 R/W 0
Writing to this register with a valid address and R/WB bit initiates an internal operation cycle to the indirect registers. R/WB: = 0: write the data to the specified indirect register. = 1: read the data from the specified indirect register. A[6:0]: Specify the address of the indirect registers (from 20H to 7FH) for the microprocessor access. E1 TPLC Channel Indirect Data Buffer (063H, 0E3H, 163H, 1E3H, 263H, 2E3H, 363H, 3E3H) Bit No. Bit Name Type Default 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
This register hold the value which will be read from or write into the indirect registers (from 20H to 7FH). If data are to be written to the indirect registers, the byte to be written must be written into this register before the target indirect register's address and R/WB=0 is written into the Address/ Control register, initiating the access. If data are to be read from the indirect registers, only the target indirect register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 490 ns, this register will contain the requested data byte. TPLC Indirect Registers Map Per-TS Control Byte for TS0 ~ TS31 IDLE Code Byte for TS0 ~ TS31 Signaling /PCM Control Byte for TS1 ~ TS31
20H ~3FH 40H ~5FH 61H ~7FH
184
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 TPLC Per-TS Control Registers (TPLC Indirect Registers 20H - 3FH) Bit No. Bit Name Type Default 7 SUBS R/W X 6 Reserved 5 DS1 R/W X 4 DS0 R/W X 3 TEST R/W X 2 LOOP R/W X 1 Reserved 0
SUBS, DS1, DS0: The SUBS, DS[1:0] bits select one of the operation to the corresponding timeslot: SUBS DS[1] DS[0] OPERATION 0 0 0 No change to the timeslot 0 1 0 Invert the odd bits (1, 3, 5, 7) of the timeslot (bit 1 is the LSB) 0 0 1 Invert the even bits (2, 4, 6, 8) of the timeslot (bit 8 is the MSB) 0 1 1 Invert all the bits of the timeslot 1 0 Replace the timeslot with the IDLE code 1 0 1 Replace the timeslot with the A-law digital milliwatt pattern (per G.711) 1 1 1 Replace the timeslot with the -law digital milliwatt pattern (per G.711) TEST: = 0: disable the data in the corresponding timeslot to be tested by PRGD. = 1: enable the data in the corresponding timeslot to be extracted to PRGD for test (when the RXPATGEN [b2, E1-00CH] is logic 1), or enable the test pattern from PRGD to replace the data in the corresponding timeslot for test (when the RXPATGEN [b2, E1-00CH] is logic 0). All the timeslots that are extracted to the PRGD are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all timeslots set to be replaced with PRGD test pattern data are concatenated replaced by the PRBS. LOOP: = 0: disable the payload loopback. = 1: enable the payload loopback. When the Receive Clock Master modes are enabled, the Elastic Store is used to align the receive line data to the data to be transmitted. When Receive Clock Slave modes are enabled, the Elastic Store is unavailable to facilitate the payload loopbacks, and loopback functionality is provided only when the transmit path is also in Transmit Clock Slave mode, and the received clock and the clock to be transmitted and Common Frame Pulse are identical (RSCCK = TSCCKB, RSCFS = TSCFS). The priority of the TPLC operation on the TSDn pin from high to low is: Extract data to PRGD for test; Payload loopback; Replace the data with the milliwatt pattern; Replace the data with the pattern generated in the PRGD; Replace the data with the value in the IDLE[7:0]; Invert the even bits or/and odd bits.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 TPLC IDLE Code Byte Registers (TPLC Indirect Registers 40H - 5FH) Bit No. Bit Name Type Default 7 IDLE7 R/W X 6 IDLE6 R/W X 5 IDLE5 R/W X 4 IDLE4 R/W X 3 IDLE3 R/W X 2 IDLE2 R/W X 1 IDLE1 R/W X 0 IDLE0 R/W X
They contain the data that will replace the data input from the TSDn pin when the corresponding SUBS and DS[1:0] are allowed. IDLE7 is the MSB. E1 TPLC Signaling / PCM Control Byte Registers (TPLC Indirect Registers 61H - 7FH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 SIGSRC R/W X 3 A R/W X 2 B R/W X 1 C R/W X 0 D R/W X
SIGSRC: This bit is valid only if the Channel Associated Signaling (CAS) is selected in the E1 FRMG Configuration Register. = 0: use the data on the TSSIGn pin as the signaling. = 1: use the data in the A, B, C, D bits as the signaling. A, B, C, D: They contain the data that can be used as signaling when the corresponding SIGSRC is logic 1. They are in the least significant nibble.
186
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RCRB Configuration (COSS = 0) (064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H) Bit No. Bit Name Type Default 7 Reserved 6 COSS R/W 0 5 SIGE R/W 0 4 3 Reserved 2 1 0 PCCE R/W 0
COSS: = 0: allow the RCRB registers to access the indirect registers. = 1: allow the RCRB registers to reflect the change of the signaling of its corresponding timeslot. SIGE: = 0: disable generation of an interrupt on the INT pin when there is a signaling change in any one of the 30 timeslots. = 1: enable generation of an interrupt on the INT pin when there is a signaling change in any one of the 30 timeslots. PCCE: = 0: the per-TS functions in RCRB are disabled. = 1: the per-TS functions in RCRB are enabled. E1 RCRB Timeslot Indirect Status (COSS = 0) (065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H) Bit No. Bit Name Type Default 7 BUSY R 0 6 5 4 3 Reserved 2 1 0
BUSY: = 0: no reading or writing operation on the indirect registers. = 1: an internal indirect register is being accessed, any new operation on the internal indirect register is not allowed. This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 490ns. No operations to the indirect registers can be done until this bit is cleared.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RCRB Timeslot Indirect Address / Control (COSS = 0) (066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H) Bit No. Bit Name Type Default 7 R/WB R/W 0 6 A6 R/W 0 5 A5 R/W 0 4 A4 R/W 0 3 A3 R/W 0 2 A2 R/W 0 1 A1 R/W 0 0 A0 R/W 0
R/WB: = 0: write the data to the specified indirect register. = 1: read the data from the specified indirect register. A[6:0]: Specified the address of the indirect registers (from 20H to 5FH) for the microprocessor access. E1 RCRB Timeslot Indirect Data Buffer (COSS = 0) (067H, 0E7H, 167H, 1E7H, 267H, 2E7H, 367H, 3E7H) Bit No. Bit Name Type Default 7 D7 R/W X 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X
This register holds the value which will be read from or written to the indirect registers (from 20H to 7FH). If data are to be written to the indirect registers, the byte to be written must be written into this register before the target indirect register's address and R/WB=0 is written into the Address/ Control register, initiating the access. If data are to be read from the indirect registers, only the target indirect register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 490 ns, this register will contain the requested data byte.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 RCRB Change of Signaling State (COSS = 1) (064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H) Bit No. Bit Name Type Default 7 Reserved 6 COSS R/W 0 5 COSS[30] R X 4 COSS[29] R X 3 COSS[28] R X 2 COSS[27] R X 1 COSS[26] R X 0 COSS[25] R X
COSS: = 0: allow the RCRB registers to access the indirect registers. = 1: allow the RCRB registers to reflect the change of the signaling of its corresponding timeslot. COSSn: = 0: the signaling in its corresponding timeslot is not changed. = 1: the signaling in its corresponding timeslot is changed. These bits are cleared to 0 after the register is read. COSS[30:25] correspond to timeslots 31 to 26. E1 RCRB Change of Signaling State (COSS = 1) (065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H) Bit No. Bit Name Type Default 7 COSS[24] R X 6 COSS[23] R X 5 COSS[22] R X 4 COSS[21] R X 3 COSS[20] R X 2 COSS[19] R X 1 COSS[18] R X 0 COSS[17] R X
COSSn: = 0: the signaling in its corresponding timeslot is not changed. = 1: the signaling in its corresponding timeslot is changed. These bits are cleared to 0 after the register is read. COSS[24:17] correspond to timeslots 25 to 18. E1 RCRB Change of Signaling State (COSS = 1) (066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H) Bit No. Bit Name Type Default 7 COSS[16] R X 6 COSS[15] R X 5 COSS[14] R X 4 COSS[13] R X 3 COSS[12] R X 2 COSS[11] R X 1 COSS[10] R X 0 COSS[9] R X
COSSn: = 0: the signaling in its corresponding timeslot is not changed. = 1: the signaling in its corresponding timeslot is changed. These bits are cleared to 0 after the register is read. COSS[16] corresponds to timeslots 17. COSS[15:9] correspond to timeslot 15 to 9. E1 RCRB Change of Signaling State (COSS = 1) (067H, 0E7H, 167H, 1E7H, 267H, 2E7H, 367H, 3E7H) Bit No. Bit Name Type Default 7 COSS[8] R X 6 COSS[7] R X 5 COSS[6] R X 4 COSS[5] R X 3 COSS[4] R X 2 COSS[3] R X 1 COSS[2] R X 0 COSS[1] R X
COSSn: = 0: the signaling in its corresponding timeslot is not changed. = 1: the signaling in its corresponding timeslot is changed. These bits are cleared to 0 after the register is read. COSS[8:1] correspond to timeslots 8 to 1.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
RCRB Indirect Registers Map 20H 01H ~ 0FH / 21H ~ 2FH 10H, 30H 11H ~ 1FH / 31H ~ 3FH 40H ~ 5FH Signaling Data Register for TS1 ~ 15 Signaling Data Register for TS17 ~31 TS0 ~ 31 Configuration Data
E1 RCRB Timeslot / Channel Signaling Data Registers (COSS = 0) (RCRB Indirect Registers 01H - 1FH / 21H - 3FH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 A R X 2 B R X 1 C R X 0 D R X
A, B, C, D: They contain the signaling of the corresponding timeslot. The value for TS0 and TS16 are not valid. There is a maximum 2 ms delay between the transition of the COSS[n] bit (E1-064H & E1-065H & E1-066H & E1-067H) and the updating of the A, B, C, D code in the corresponding indirect registers 21H ~ 3FH. To avoid this 2ms delay, users can read the corresponding b3~0 in the indirect registers 01H ~ 1FH first. If the value of these four bits are different from the previous A, B, C, D code, then the content of b3~0 in the 01H ~ 1FH is the updated A, B, C, D code. If the conternt of the four bits is the same as the previous A, B, C, D code, then users should read the b3~0 in the 21H ~ 3FH to get the updated A, B, C, D code. E1 RCRB Per-Timeslot Configuration Registers (COSS = 0) (RCRB Indirect Registers 40H - 5FH) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 DEB R/W X
DEB: = 0: disable signaling debounce. = 1: enable signaling debounce (valid only if the PCCE is logic 1). That is, the signaling is acknowledged only when 2 consecutive signaling of a timeslot are the same.
190
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 PMON Interrupt Enable / Status (068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 INTE R/W 0 1 XFER R 0 0 OVR R 0
INTE: = 0: disable the interrupt on the INT pin when the counter data has been transferred into the Error Count registers. = 1: enable the interrupt on the INT pin when the counter data has been transferred into the Error Count registers. XFER: = 0: indicate that the counter data has not been transferred to the Error Count registers. = 1: indicate that the counter data has been transferred to the Error Count registers. This bit is clear to 0 after the bit is read. OVR: = 0: indicate that no overwritten on the Error Count registers has occurred. = 1: indicate that one of the Error Count registers is overwritten. This bit is clear to 0 after the bit is read. Registers 069H-06DH, 0E9H-0EDH, 16H-16DH, 1E9H-1EDH, 269H-26DH,2E9H-2EDH ,369H-36DH, 3E9H-3EDH: The PMON Error Count registers for a single framer are updated as a group by writing to any of the PMON count registers or updated every 1 second when the AUTOUPDATE (b0, E1-000H) is set. The PMON Error Count registers for eight framers are updated by writing to the Chip ID/ Global PMON Update register (E1-009H). When the chip is reset, the contents of the PMON Error Count registers are unknown until the first latching of performance data is performed. E1 PMON Framing Bit Error Count (069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H) Bit No. Bit Name Type Default 7 Reserved 6 FER[6] R X 5 FER[5] R X 4 FER[4] R X 3 FER[3] R X 2 FER[2] R X 1 FER[1] R X 0 FER[0] R X
These bits are valid when it is in the Basic Frame Sync. They represent the number of the basic frame alignment signal errors and update on the defined intervals. The basic frame alignment signal errors are defined in the WORDERR (b5, E1-000H) and the CNTNFAS (b4, E1-000H).
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 PMON Far End Block Error Count LSB (06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH) Bit No. Bit Name Type Default 7 FEBE[7] R X 6 FEBE[6] R X 5 FEBE[5] R X 4 FEBE[4] R X 3 FEBE[3] R X 2 FEBE[2] R X 1 FEBE[1] R X 0 FEBE[0] R X
E1 PMON Far End Block Error Count MSB (06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 1 FEBE[9] R X 0 FEBE[8] R X
The FEBE[9:0] are valid when it is in the CRC Multi-Frame Sync. They represent the number of the Far End Block Errors (FEBE) and update on the defined intervals. E1 PMON CRC Error Count LSB (06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH) Bit No. Bit Name Type Default 7 CRCE[7] R X 6 CRCE[6] R X 5 CRCE[5] R X 4 CRCE[4] R X 3 CRCE[3] R X 2 CRCE[2] R X 1 CRCE[1] R X 0 CRCE[0] R X
E1 PMON CRC Error Count MSB (06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 1 CRCE[9] R X 0 CRCE[8] R X
The CRCE[9:0] are valid when it is in the CRC Multi-Frame Sync. They represent the number of the CRC errors and update on the defined intervals.
192
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 PRGD Control (070H) Bit No. Bit Name Type Default 7 PDR[1] R/W 0 6 PDR[0] R/W 0 5 Reserved 4 PS R/W 0 3 TINV R/W 0 2 RINV R/W 0 1 AUTOSYNC R/W 1 0 MANSYNC R/W 0
PDR[1:0]: The PDR[1:0] define the function of the four PRGD Pattern Detector registers: PDR[1:0] PRGD Pattern Detector Registers (#1 ~ #4) 00, 01 Pattern Receive 10 Error Count 11 Bit Count (The #1 is the LSB, while the #4 is the MSB.) PS: = 0: a pseudo-random pattern is generated/detected by the PRGD. = 1: a repetitive pattern is generated/detected by the PRGD. This bit should be set first of all the PRGD registers. TINV: = 0: disable the inversion of the generated pattern before being transmitted. = 1: enable the inversion of the generated pattern before being transmitted. RINV: = 0: disable the inversion of the received pattern before being processed. = 1: enable the inversion of the received pattern before being processed. AUTOSYNC: = 0: disable automatically re-searching for the sync of the pattern when the PRGD pattern is out of synchronization. = 1: enable automatically re-searching for the sync of the pattern when the PRGD pattern is out of synchronization. MANSYNC: Trigger on the rising edge. A transition from logic 0 to logic 1 on this bit manually initiates a re-search for the sync of a pattern. Every time when the setting of the PRGD registers is changed or the detector data source changes, a manual sync operation is recommended to ensure that the detector works correctly.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 PRGD Interrupt Enable / Status (071H) Bit No. Bit Name Type Default 7 SYNCE R/W 0 6 BEE R/W 0 5 XFERE R/W 0 4 SYNCV R X 3 SYNCI R X 2 BEI R X 1 XFERI R X 0 OVR R X
SYNCE: = 0: disable the interrupt on the INT pin when the SYNCI is logic one. = 1: enable the interrupt on the INT pin when the SYNCI is logic one. BEE: = 0: disable the interrupt on the INT pin when bit error has been detected in the received pattern. = 1: enable the interrupt on the INT pin when each bit error is detected in the received pattern. XFERE: = 0: disable the interrupt on the INT pin when the the data in the PRGD pattern detector register is updated. = 1: enable the interrupt on the INT pin when the the data in the PRGD pattern detector register is updated. SYNCV: = 0: the pattern is out of sync (the pattern detector has detected 10 or more bit errors in a hopping 48-bit window). = 1: the pattern is in sync (the pattern detector has observed at least 48 consecutive error-free bit-periods). SYNCI: = 0: there is no transition on the SYNCV. = 1: there is a transition (from 0 to 1 or from 1 to 0) on the SYNCV. This bit is cleared to 0 after the bit is read. BEI: = 0: no bit error is detected in the received pattern. = 1: at least one bit error has been detected in the received pattern. This bit is cleared to 0 after the bit is read. XFERI: = 0: the data in the PRGD pattern detector register is not updated. = 1: the data in the PRGD pattern detector register is updated. This bit is cleared to 0 after the bit is read. OVR: = 0: the PRGD pattern detector register is not overwritten. = 1: the PRGD pattern detector register is overwritten. This bit is cleared to 0 after the bit is read.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 PRGD Shift Register Length (072H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 PL[4] R/W 0 3 PL[3] R/W 0 2 PL[2] R/W 0 1 PL[1] R/W 0 0 PL[0] R/W 0
These bits determine the length of the valid data in the PRGD pattern insertion register. The length is equal to the value of PL[4:0] + 1. E1 PRGD Tap Bit Type Function Default (073H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 PT[4] R/W 0 3 PT[3] R/W 0 2 PT[2] R/W 0 1 PT[1] R/W 0 0 PT[0] R/W 0
These bits determine the feedback tap position of the generated pseudo random pattern before it is transmitted. The feedback tap position is equal to the value of PT[4:0] + 1. In application, the PT is always less than the PL. E1 PRGD Error Insertion (074H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 EVENT R/W 0 2 EIR[2] R/W 0 1 EIR[1] R/W 0 0 EIR[0] R/W 0
EVENT: A single bit error is generated when the state of this bit is changed from 0 to 1. To insert another bit error, this bit must be cleared to 0, and then set from 0 to 1 again. EIR[2:0]: The EIR[2:0] bits determine the bit error rate that will be inserted in the PRGD test pattern. If the bit error rate is changed from one non- zero value to another non-zero value, it is recommended to set the EIR[2:0] to `000' first, then set the EIR[2:0] to the desired value. EIR[2:0] Bit error rate 000 No error inserted 001 No error inserted 010 10-2 011 10-3 100 10-4 101 10-5 110 10-6 111 10-7
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 PRGD Pattern Insertion #1 (078H) Bit No. Bit Name Type Default 7 PI[7] R/W 0 6 PI[6] R/W 0 5 PI[5] R/W 0 4 PI[4] R/W 0 3 PI[3] R/W 0 2 PI[2] R/W 0 1 PI[1] R/W 0 0 PI[0] R/W 0
E1 PRGD Pattern Insertion #2 (079H) Bit No. Bit Name Type Default 7 PI[15] R/W 0 6 PI[14] R/W 0 5 PI[13] R/W 0 4 PI[12] R/W 0 3 PI[11] R/W 0 2 PI[10] R/W 0 1 PI[9] R/W 0 0 PI[8] R/W 0
E1 PRGD Pattern Insertion #3 (07AH) Bit No. Bit Name Type Default 7 PI[23] R/W 0 6 PI[22] R/W 0 5 PI[21] R/W 0 4 PI[20] R/W 0 3 PI[19] R/W 0 2 PI[18] R/W 0 1 PI[17] R/W 0 0 PI[16] R/W 0
E1 PRGD Pattern Insertion #4 (07BH) Bit No. Bit Name Type Default 7 PI[31] R/W 0 6 PI[30] R/W 0 5 PI[29] R/W 0 4 PI[28] R/W 0 3 PI[27] R/W 0 2 PI[26] R/W 0 1 PI[25] R/W 0 0 PI[24] R/W 0
When a repetitive pattern is selected to transmit, the data in these registers are the repetitive pattern. When a pseudo random pattern is selected to transmit, the data in these registers should be set to FFFFFFFFH. They are the initial value for the pseudo random pattern. Writing to PI[31:24] updates the PRGD configuration. When a repetitive pattern is transmitted, the PI[31] bit is transmitted first, followed by the remaining bits in sequence down to PI[0]. The length of the valid data in these four registers is determined by the PL[4:0]. When the length is less than 31, the bits in higher PI are not used.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
E1 PRGD Pattern Detector #1 (07CH) Bit No. Bit Name Type Default 7 PD[7] R X 6 PD[6] R X 5 PD[5] R X 4 PD[4] R X 3 PD[3] R X 2 PD[2] R X 1 PD[1] R X 0 PD[0] R X
E1 PRGD Pattern Detector #2 (07DH) Bit No. Bit Name Type Default 7 PD[15] R X 6 PD[14] R X 5 PD[13] R X 4 PD[12] R X 3 PD[11] R X 2 PD[10] R X 1 PD[9] R X 0 PD[8] R X
E1 PRGD Pattern Detector #3 (07EH) Bit No. Bit Name Type Default 7 PD[23] R X 6 PD[22] R X 5 PD[21] R X 4 PD[20] R X 3 PD[19] R X 2 PD[18] R X 1 PD[17] R X 0 PD[16] R X
E1 PRGD Pattern Detector #4 (07FH) Bit No. Bit Name Type Default 7 PD[31] R X 6 PD[30] R X 5 PD[29] R X 4 PD[28] R X 3 PD[27] R X 2 PD[26] R X 1 PD[25] R X 0 PD[24] R X
When the PDR[1:0] (b7~6, E1-070H) are set to 00 or 01, the four PRGD pattern detector registers are configured as Pattern Receive registers. They reflect the content of the received pattern. When the PDR[1:0] (b7~6, E1-070H) are set to 10, the four PRGD pattern detector registers are configured as Error Counter registers. The value in these registers represents the number of the bit errors. The bit errors are not accumulated when the pattern is out of sync. When the PDR[1:0] (b7~6, E1-070H) are set to 11, the four PRGD pattern detector registers are configured as Bit Counter registers. The value in these registers represent the total received bit number. These registers can be configured to update every second automatically when the AUTOUPDATE (b0, E1-000H) is set to 1, or by writing to any of these four registers, or to the Revision / Chip ID / Global PMON register.
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
5.2.2
T1 / J1 MODE
T1 / J1 Receive Line Options (000H, 080H, 100H, 180H, 200H, 280H, 300H, 380H) Bit No. Bit Name Type Default 7 FIFOBYP R/W 0 6 UNF R/W 0 5 IBCD_IDLE R/W 0 4 Reserved 3 AUTOYELLOW R/W 0 2 AUTORED R/W 0 1 AUTOOOF R/W 0 0 AUTOUPDATE R/W 0
FIFOBYP: This bit decides whether the received data should pass through or bypass the Receive Jitter Attenuation FIFO. = 0: The received data pass through the RJAT FIFO. = 1: The RJAT FIFO is bypassed. The delay is reduced by typically 24 bits. UNF: = 0: The Frame Processor operates normally. = 1: Frame searching is disabled, the RCRB holds its signaling frozen, and Auto_OOF function, if enabled, will consider OOF to be declared. IBCD_IDLE: This bit is valid in framed mode. = 0: compare the inband loopback activate/deactivate code with all received data stream, including the F-bit. However, the result of F-bit comparison is discarded. = 1: compare the inband loopback activate/deactivate code with the received data stream, excluding the F-bit. AUTOYELLOW: This bit decides whether to send the Yellow Alarm signal automatically. = 0: The automatic Yellow Alarm Transmission is disabled. It means that the Yellow Alarm can only be transmitted when the XYEL (b1, T1/J1045H) is set to 1. = 1: The automatic Yellow Alarm Transmission is enabled. It means that the Yellow Alarm will be transmitted automatically when Red alarm is declared in the received data stream. AUTORED: This bit decides whether to start trunk conditioning (replacing data on RSDn/MRSD with the data stored in the data trunk conditioning registers in RPLC) automatically when Red Alarm is declared. = 0: The trunk conditioning is not activated automatically when Red Alarm is declared in the Alarm Detector block. = 1: The trunk conditioning will be initiated automatically when Red Alarm is declared in the Alarm Detector block. AUTOOOF: This bit decides whether to start trunk conditioning (replacing data on RSDn/MRSD with the data stored in the data trunk conditioning registers in RPLC) automatically in the duration of loss of SF/ESF frame. = 0: The trunk conditioning is not activated automatically when the INFR (b0, T1/J1-022H) is declared in the Frame Processor block. = 1: The trunk conditioning will be activated automatically when the INFR (b0, T1/J1-022H) is declared in the Frame Processor block. AUTOUPDATE: This bit decides whether the PMON and PRGD registers are automatically updated once every second. = 0: The PMON and PRGD registers are not automatically updated. They can only be updated by MCU operation. = 1: The PMON and PRGD registers will be automatically updated once every second.
198
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Receive Side System Interface Options (001H, 081H, 101H, 181H, 201H, 281H, 301H, 381H) Bit No. Bit Name Type Default 7 IMODE[1] R/W 1 6 IMODE[0] R/W 1 5 RSCKSEL R/W 0 4 RSCCK2M R/W 0 3 RSCCK8M R/W 0 2 RSFSP R/W 0 1 ALTIFP R/W 0 0 IMTKC R/W 0
IMODE[1:0]: These bits select the operation mode in the receive path. IMODE[1:0] Operation Mode In Receive Path 00 Receive Clock Master Fractional T1/J1 mode 01 Receive Clock Master Full T1/J1 mode 10 Receive Clock Slave RSCK Reference mode 11 Receive Clock Slave External Signaling mode "Receive Clock Master Full T1/J1" mode means that the received entire frame (193 bits) is clocked out from RSDn pin, and there are no gaps in the RSCKn clock pulse. "Receive Clock Master Fractional T1/J1" mode means that the RSCKn only clocks out on the selected channels, and RSCKn does not pulse during those un-selected channels. The selection of the channel is decided by the EXTRACT (b2, T1/J1-RPLC-Indirect Register-01-18 H). When Receive Clock Slave RSCK Reference Mode is selected, the RSCKn/RSSIGn pin will be used as RSCKn to output a 1.544 MHz jitter attenuated version of LRCKn or an 8KHz clock. When Receive Clock Slave External Signaling mode is selected, the RSCKn/RSSIGn pin is used as RSSIGn to output the extracted signaling data. Each channel's signaling data is channel aligned with the RSDn data stream and located in lower nibble (b5b6b7b8) of the timeslot. RSCKSEL: When Receive Clock Slave RSCK Reference Mode is selected, this bit selects the frequency of the RSCKn. = 0: the RSCKn outputs an 8 KHz timing reference that is generated by dividing the jitter attenuated version of LRCKn. = 1: the RSCKn outputs a jitter attenuated version of the 1.544MHz receive line clock (LRCK). RSCCK2M, RSCCK8M: These bits determine the bit rate of the received data stream on the backplane. The 2.048 Mbit/s rate can only be supported when the backplane is configured in Receive Clock Slave mode. If the Receive Multiplexed mode is desired, all the RSCCK2M & RSCCK8M in eight framers must be set the same to select the 8.192 Mbit/s backplane bit rate. When the RSCCK2M, RSCCK8M selects the 8.192 Mbit/s, the IMODE[1:0] (b7~6, T1/J1001H) must be set to 11. RSCCK2M, RSCCK8M Backplane Rate 00 1.544M bit/s 10 2.048M bit/s 01 8.192M bit/s 11 Reserved RSFSP, ALTIFP: RSFSP ALTIFP RSFSn Indication 0 0 the RSFSn pin asserts on each F-bit. 0 1 the RSFSn pin asserts on every second F-bit (i.e., the F-bit of even frame if there is no channel offset). 1 0 the signal on the RSFSn pin asserts on the first F-bit of every 12 frames (in SF format) or every 24 frames (in ESF format). 1 1 In Receive Multiplexed mode, regardless of the setting in the RSFSP and the ALTRSFS, the MRSFS can only indicate each F-bit of SF/ESF of the selected first framer.
199
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
IMTKC: This bit decides how to substitute the received data stream on RSDn and RSSIGn with contents in RPLC Data Trunk Conditioning Registers and RPLC Signaling Trunk Conditioning Registers. This bit affects the corresponding timeslot of the MRSD and MRSSIG even if the multiplexed backplane is enabled. = 0: The data and signaling signals are substituted on a per-timeslot basis in accordance with the control bits contained in the per-timeslot Payload Control Byte registers in the RPLC. = 1: the data on RSDn of all timeslots are replaced with the data contained in the Data Trunk Conditioning registers in RPLC, and the data on RSSIGn of all timeslots are replaced with the data contained in the Signaling Trunk Conditioning registers. To enable this function, the PCCE (b0, T1/ J1-050H) of the RPLC must be set to logic 1. T1 / J1 Backplane Parity Configuration / Status (002H, 082H, 102H, 182H, 202H, 282H, 302H, 382H) Bit No. Bit Name Type Default 7 TPTYP R/W 0 6 TPRTYE R/W 0 5 TSDI R X 4 TSSIGI R X 3 PTY_EXTD R/W 0 2 Reserved 1 RPTYP R/W 0 0 RPRTYE R/W 0
TPTYP: = 0: even parity check is employed in the F-bit input from the TSDn/MTSD and TSSIGn/MTSSIG pin, which means a logic one is expected in the F-bit position when the number of ones in the previous SF/ESF is odd. = 1: odd parity check is employed in the F-bit input from the TSDn/MTSD and TSSIGn/MTSSIG pin, which means a logic one is expected in the Fbit position when the number of ones in the previous SF/ESF is even. TPRTYE: This bit is invalid in Receive Clock Master Fractional T1/J1 mode. = 0: disable the interrupt on the INT pin when a parity error is detected on the TSDn/MTSD pin or a parity error is detected on the TSSIGn/ MTSSIG pin. = 1: enable the interrupt on the INT pin when a parity error is detected on the TSDn/MTSD pin or a parity error is detected on the TSSIGn/MTSSIG pin. TSDI: = 0: indicate that no parity error is detected on the TSDn/MTSD pin. = 1: indicate that a parity error is detected on the TSDn/MTSD pin. This bit is cleared to 0 after the bit is read. TSSIGI: = 0: indicate that no parity error is detected on the TSSIGn/MTSSIG pin. = 1: indicate that a parity error is detected on the TSSIGn/MTSSIG pin. This bit is cleared to 0 after the bit is read. PTY_EXTD: = 0: the parity is calculated over the previous SF/ESF, excluding the F-bit on the TSDn/MTSD, TSSIGn/MTSSIG, RSDn/MRSD and RSSIGn/ MRSSIG pin. = 1: the parity is calculated over the previous SF/ESF, including the F-bit on the TSDn/MTSD, TSSIGn/MTSSIG, RSDn/MRSD and RSSIGn/ MRSSIG pin. RPTYP: This bit is invalid in Receive Clock Master Fractional T1/J1 mode and valid when the RPRTYE = 1. = 0: even parity check is employed in the F-bit output on the RSDn/MRSD and RSSIGn/MRSSIG pin, which means a logic one should be replaced in the F-bit when the number of ones in the previous SF/ESF is odd. = 1: odd parity check is employed in the F-bit output on the RSDn/MRSD and RSSIGn/MRSSIG pin, which means a logic one should be replaced in the F-bit when the number of ones in the previous SF/ESF is even. RPRTYE: This bit is invalid in Receive Clock Master Fractional T1/J1 mode. = 0: disable the parity on the RSDn/MRSD and RSSIGn/MRSSIG pin. = 1: enable the parity on the RSDn/MRSD and RSSIGn/MRSSIG pin.
200
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Receive Interface Configuration (003H, 083H, 103H, 183H, 203H, 283H, 303H, 383H) Bit No. Bit Name Type Default 7 MRBS R/W 0 6 MRBC R/W 0 5 TRI[1] R/W 0 4 TRI[0] R/W 0 3 RSCKRISE R/W 0 2 LRCKFALL R/W 0 1 RSCFSFALL R/W 0 0 RSCCKRISE R/W 0
MRBS: In Receive Multiplexed mode, this bit decides which bus the corresponding framer will use to output the received data. = 0: The first multiplexed bus (MRSD[1], MRSFS[1], MRSSIG[1]) is selected. = 1: The second multiplexed bus (MRSD[2], MRSFS[2], MRSSIG[2]) is selected. MRBC: This bit turns on or turn off the transmission of received data from the corresponding framer to the selected multiplexed receive bus. Users should complete the setting in the MRBS (b7, T1/J1-003H) before turn on this bit. = 0: The corresponding framer will not output its data stream on the multiplexed bus. = 1: The corresponding framer will output its data stream on the multiplexed bus. TRI[1:0]: These bits decide the output status of the RSDn/MRSD and RSSIGn/MRSSIG pins. TRI[1:0] Output Status on the RSDn/MRSD and RSSIGn/MRSSIG pin 00 in high impedance 10 Reserved 01 Normal operation 11 Reserved RSCKRISE: This bit selects the active edge of RSCKn to update the data on the corresponding RSDn and RSFSn.This bit is valid in Receive Clock Master mode. = 0: the falling edge is selected. = 1: the rising edge is selected. LRCKFALL: This bit selects the active edge of LRCKn to sample the data on the corresponding LRDn. = 0: the rising edge is selected. = 1: the falling edge is selected. RSCFSFALL: This bit selects the active edge of RSCCK/MRSCCK to sample the data on the corresponding RSCFS/MRSCFS. This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode. = 0: the rising edge is selected. = 1: the falling edge is selected This bit in all eight framers must be set to the same value. RSCCKRISE: This bit selects the active edge of RSCCK/MRSCCK to update the data on the corresponding RSDn/MRSD, RSSIGn/MRSSIG and RSFSn/ MRSFS. This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode. = 0: the falling edge is selected. = 1: the rising edge is selected. In Receive Multiplexed mode, the RSCCKRISE of the eight framers must be set to the same value.
201
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Transmit Interface Configuration (004H, 084H, 104H, 184H, 204H, 284H, 304H, 384H) Bit No. Bit Name Type Default 7 FIFOBYP R/W 0 6 TAISEN R/W 0 5 Reserved 4 3 TSCCKBFALL R/W 0 2 TSFSRISE R/W 0 1 TSDFALL R/W 0 0 LTCKRISE R/W 0
FIFOBYP: This bit decides whether the transmit data should pass through or bypass the Transmit Jitter Attenuation FIFO. The bit is valid in Clock Slave mode. = 0: the data to be transmitted pass through the TJAT FIFO. = 1: the TJAT FIFO is bypassed. The delay is reduced by typically 24 bits. TAISEN: This bit enables the line interface to generate an un-framed all-ones Alarm Indication Signal on the TLDn pin or the corresponding framer on the MTLD. = 0: normal operation. = 1: TLDn or the corresponding framer on the MTLD transmits all ones. TSCCKBFALL: This bit selects the active edge of TSCCKB/MTSCCKB to sample the data on the corresponding TSDn/MTSD, TSSIGn/MTSSIG and TSCFS/ MTSCFS. This bit is valid in Transmit Clock Slave mode and Transmit Multiplexed mode. = 0: the rising edge is selected. = 1: the falling edge is selected. The TSCCKBFALL of the eight framers should be set to the same value. TSFSRISE: This bit is valid in Transmit Clock Slave TSFS Enabled mode and Transmit Clock Master mode. = 0: In Transmit Clock Slave TSFS Enabled mode, the signal on the TSFSn pin is updated on the falling edge of the TSCCKB. In Transmit Clock Master mode, the signal on the TSFSn pin is updated on the falling edge of the LTCKn. = 1: In Transmit Clock Slave TSFS Enabled mode, the signal on the TSFSn pin is updated on the rising edge of the TSCCKB. In Transmit Clock Master mode, the signal on the TSFSn pin is updated on the rising edge of the LTCKn. TSDFALL: This bit selects the active edge of LTCKn to sample the data on the corresponding TSDn in Transmit Clock Master mode. = 0: the TSDn is sampled on the rising edge of the LTCKn. = 1: the TSDn is sampled on the falling edge of the LTCKn. LTCKRISE: This bit selects the active edge of LTCKn to update the data on the corresponding LTDn. = 0: the falling edge is selected. = 1: the rising edge is selected.
202
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Transmit Side System Interface Options (005H, 085H, 105H, 185H, 205H, 285H, 305H, 385H) Bit No. Bit Name Type Default EMODE[1:0]: EMODE[1:0] Operation Mode In Transmitter Path 00 Reserved 01 Transmit Clock Master mode 10 Transmit Clock Slave TSFS Enable mode 11 Transmit Clock Slave External Signaling mode In Transmit Multiplexed mode, these bits must be set to 11. FPINV: = 0: the positive pulse on the TSCFS/MTSCFS pin is valid. = 1: the negative pulse on the TSCFS/MTSCFS pin is valid. This bit of the eight framers should be set to the same value. ABXXEN: This bit is valid only in T1 ESF mode. = 0: the valid signaling on the TSSIGn/MTSSIG pin is in the lower four nibble of each channel (i.e. XXXXABCD). = 1: the valid signaling on the TSSIGn/MTSSIG pin is in the upper two-bit positions of the lower nibble of each channel (i.e. XXXXABXX). Thus, the `A' bit will be inserted to the signaling bit of Frame 6 and 18, and the `B' bit will be inserted to the signaling bit of Frame 12 and 24. RATE[1:0]: These bits determine the bit rate of the transmit data stream on the backplane. Note that if any of the eight framers selects the 8.192 Mbit/s backplane bit rate, the multiplxed bus will be enabled for the chip. When the RATE[1:0] selects the 2.048 Mbit/s or 8.192 Mbit/s, the EMODE[1] (b7, T1/J1-005H) must be set to 1 (i.e., in Transmit Clock Slave mode). RATE[1:0] Backplane Rate 00 1.544M bit/s 01 2.048M bit/s 10 Reserved 11 8.192M bit/s TSCFSP: = 0: indicate that the signal on the TSCFS pin asserts on each F-bit. = 1: indicate that the signal on the TSCFS pin asserts on the first F-bit of every 12 SFs or every 24 ESFs. This bit of the eight framers should be set to the same value. 7 EMODE[1] R/W 1 6 EMODE[0] R/W 1 5 FPINV R/W 0 4 ABXXEN R/W 0 3 RATE[1] R/W 0 2 RATE[0] R/W 0 1 TSCFSP R/W 0 0 Reserved
203
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Transmit Framing and Bypass Options (006H, 086H, 106H, 186H, 206H, 286H, 306H, 386H) Bit No. Bit Name Type Default 7 FRESH R/W 0 6 Reserved 5 SIGAEN R/W 0 4 Reserved 3 FDIS R/W 0 2 FBITBYP R/W 0 1 CRCBYP R/W 0 0 FDLBYP R/W 0
FRESH: = 0: normal operation. = 1: initiate the FIFO in the Frame Generator block. After initialization of the backplane interface, the user should write 1 into this bit and then clear it. SIGAEN: = 0: track the signaling input from the TSSIGn/MTSSIG pin for the signaling bit. = 1: take a snapshot of the 1st frame input from the TSSIGn/MTSSIG pin and lock it for the signaling bit of the whole SF/ESF. FDIS: This bit is valid when the UF (b6, T1/J1-046H) is logic 0. = 0: the Frame Generator is enabled to generate and insert the framing bits into the transmit data. = 1: the Frame Generator is bypassed. Data on TSDn/MTSD pin is transmitted transparently. FBITBYP: This bit is valid when the UF (b6, T1/J1-046H) and the FDIS (b3, T1/J1-006H) are logic 0. = 0: the frame synchronization bits in the output data stream are generated by the Frame Generator. = 1: the frame synchronization bits in the input data stream on the TSDn/MTSD pin will be output transparently. CRCBYP: This bit is valid when the UF (b6, T1/J1-046H) and the FDIS (b3, T1/J1-006H) are logic 0. = 0: the framing bit corresponding to the CRC-6 bit position in the output data stream are generated by the Frame Generator. = 1: the framing bit corresponding to the CRC-6 bit position in the input data stream on the TSDn/MTSD pin will be output transparently. FDLBYP: This bit is valid when the UF (b6, T1/J1-046H) and the FDIS (b3, T1/J1-006H) are logic 0. = 0: the framing bit corresponding to the data link bit position in the output data stream are generated by the Frame Generator. = 1: the framing bit corresponding to the data link bit position in the input data stream on the TSDn/MTSD pin will be output transparently.
204
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Transmit Timing Options (007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H) Bit No. Bit Name Type Default 7 Reserved 6 5 4 3 2 1 0 TJATREF_SEL[2] TJATREF_SEL[1] TJATREF_SEL[0] LTCK_SEL[2] LTCK_SEL[1] LTCK_SEL[0] R/W R/W R/W R/W R/W R/W 1 0 0 1 0 1
TJATREF_SEL[2:0]: The TJATREF_SEL[2:0] select the input reference clock for the TJAT DPLL. TJATREF_SEL[2:0] Input Reference Clock 000 TSCCKA / 8 001 TSCCKB 010 LRCK 011 TSCCKA 100 XCK / 24 the others TSCCKB LTCK_SEL[2:0]: LTCK_SEL[2:0] 000 001 010 011 100 the others Line Transmit Clock TSCCKA / 8 TSCCKB LRCK TSCCKA XCK / 24 A smoothed clock output from the TJAT DPLL
205
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Interrupt Source #1 (008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H) Bit No. Bit Name Type Default 7 PMON R/W 0 6 IBCD R/W 0 5 FRMP R/W 0 4 PRGD R/W 0 3 ELSB R/W 0 2 RHDLC#1 R/W 0 1 RBOM R/W 0 0 ALMD R/W 0
Bits in this register indicate which function block caused an interrupt signal on INT pin. Reading this register does not clear the interrupt indication. To clear the interrupt indication on INT pin, the corresponding interrupt status register must be read. T1 / J1 Interrupt Source #2 (009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H) Bit No. Bit Name Type Default 7 RHDLC#2 R/W 0 6 PRTY R/W 0 5 TJAT R/W 0 4 RJAT R/W 0 3 THDLC#1 R/W 0 2 THDLC#2 R/W 0 1 Reserved 0 RCRB R/W 0
Bits in this register indicate which function block caused an interrupt signal on INT pin. The PRTY bit indicates a pending parity error indication needs serving in the Backplane Parity Configuration and Status registers. Reading this register does not clear the interrupt indication. To clear the interrupt indication on INT pin, the corresponding interrupt status register must be read.
206
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Diagnostics (00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 LINELB R/W 0 3 Reserved 2 DDLB R/W 0 1 TXMFP R/W 0 0 TXDIS R/W 0
LINELB: Line Loop back means that the transmit line interface data and clock (LTDn and LTCKn) are internal directly comes from the received line data and clock (LRDn and LRCKn). The loop back data stream can pass through the Receive Jitter Attenuator or bypass the Receive Jitter Attenuator (if the Receive Jitter Attenuator is configured to be bypassed) = 0: Line loop back is disabled. = 1: Line loop back is enabled. DDLB: Digital Loop back means that the received line data and clock (LRDn and LRCKn) are internal directly comes from the transmit line data and clock (LTDn and LTCKn) without the Receive Jitter Attenuator. = 0: Digital loop back is disabled. = 1: Digital loop back is enabled. TXMFP: This bit controls whether the mimic pattern is generated. The mimic pattern is a copy of the F-bit. The mimic pattern is generated in the 1st bit of each channel. = 0: the mimic pattern is not generated. = 1: the mimic pattern is generated. TXDIS: = 0: normal transmission. = 1: force the data to be transmitted on the TLDn pin to be all zeros. T1 / J1 Revision / Chip ID / Global PMON Update (00CH) Bit No. Bit Name Type Default 7 TYPE[2] R 0 6 TYPE[1] R 0 5 TYPE[0] R 0 4 ID[4] R 0 3 ID[3] R 0 2 ID[2] R 0 1 ID[1] R 0 0 ID[0] R 1
Writing to this register causes all Performance Monitor and PRGD Generator/Detector counters to be updated simultaneously. TYPE[2:0]: TYPE[2:0] are fixed to 000, representing the IDT82V2108 chip. ID[4:0]: ID[4:0] are fixed to 00011, representing the current version number of the IDT82V2108.
207
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Data Link Micro Select / Framer Reset (00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH) Bit No. Bit Name Type Default 7 6 5 4 RHDLCSEL[1] RHDLCSEL[0] THDLCSEL[1] THDLCSEL[0] R/W R/W R/W R/W X X X X 3 TXCISEL R/W X 2 Reserved 1 0 RESET R/W 0
RHDLCSEL[1:0]: The RHDLCSEL[1:0] select one of the two HDLC Receivers to be accessed by the microprocessor in ESF format. When RHDLC #1 is selected, the HDLC link position is fixed in the DL of F-bit. When RHDLC #2 is selected, the microprocessor can access the HDLC #2 controller to assign the link to any one of 24 channels. These bits must be set before using the HDLC controller. RHDLCSEL[1:0] the HDLC Receiver 00 RHDLC #1 01 RHDLC #2 10 Reserved 11 THDLCSEL[1:0]: The THDLCSEL[1:0] select which one of the two HDLC Transmitters to be accessed by the microprocessor in ESF format. When THDLC #1 is selected, the HDLC link position is fixed in the DL of F-bit. When THDLC #2 is selected, the microprocessor can access the HDLC #2 controller to assign the link to any one of 24 channels. These bits must be set before using the HDLC controller. THDLCSEL[1:0] the HDLC Transmitter 00 THDLC #1 01 THDLC #2 10 Reserved 11 TXCISEL: The registers addressed from T1/J1-070H to T1/J1-071H are shared by the HDLC Receiver and HDLC Transmitter to decide the position of the extracted bit in the received data stream and the inserted bit in the transmitting data stream respectively. This bit is used to decide whether the Read/ Write operation on the registers addressed from T1/J1-070H to T1/J1-071H is for the HDLC receiver or for the HDLC transmitter. = 0: the Read/Write operation on registers addressed from T1/J1-070H to T1/J1-071H is for HDLC receiver. = 1: Read/Write operation on registers addressed from T1/J1-070H to T1/J1-071H is for the HDLC transmitter. RESET: This bit implements a software reset for individual framer. = 0: normal operation. = 1: The corresponding framer is held in reset. However, this bit and the bits in this register can not be reset. Therefore, a logic 0 must be written to bring the framer out of reset. Holding the framer in a reset state effectively puts it into a low power standby mode. A hardware reset clears the RESET bit and the bits in this register.
208
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Interrupt ID (00EH) Bit No. Bit Name Type Default 7 INT[8] R 0 6 INT[7] R 0 5 INT[6] R 0 4 INT[5] R 0 3 INT[4] R 0 2 INT[3] R 0 1 INT[2] R 0 0 INT[1] R 0
This register indicates which one of the eight framers caused the interrupt INT pin to logic low. When any one of the eight framers caused the interrupt, the corresponding bit in the INT[8:1] will be high. T1 / J1 Pattern Generator / Detector Positioning / Control (00FH) Bit No. Bit Name Type Default 7 PRGDSEL[2] R/W 0 6 PRGDSEL[1] R/W 0 5 PRGDSEL[0] R/W 0 4 Nx56k_GEN R/W 0 3 Nx56k_DET R/W 0 2 RXPATGEN R/W 0 1 UNF_GEN R/W 0 0 UNF_DET R/W 0
The IDT82V2108 has only one Pattern Generator/Detector (PRGD) shared by all eight framers. At one time, only one framer can use this PRGD. This register selects which framer will use the PRGD and how the PRGD will be used. PRGDSEL[2:0]: PRGDSEL[2:0] select one of the eight framers to be tested by the PRGD block. PRGDSEL[2:0] Tested Framer 000 Framer 1 001 Framer 2 010 Framer 3 011 Framer 4 100 Framer 5 101 Framer 6 110 Framer 7 111 Framer 8 Nx56k_GEN: This bit is invalid when the UNF_GEN (b1, T1/J1-00FH) is logic 1. = 0: eight bits are all replaced with the PRGD pattern when one channel is selected in the TPLC or RPLC. = 1: the 7 most significant bits are replaced with the PRGD pattern when one channel is selected in the TPLC or RPLC. Nx56k_DET: This bit is invalid when the UNF_DEL (b0, T1/J1-00FH) is logic 1. = 0: eight bits are all detected by the PRGD when one channel is selected in the TPLC or RPLC. = 1: the 7 most significant bits are detected by the PRGD when one channel is selected in the TPLC or RPLC. RXPATGEN: = 0: the pattern in PRGD is generated in the transmit path and is detected in the receive path. = 1: the pattern in PRGD is generated in the receive path and is detected in the transmit path. UNF_GEN: = 0: which channels of the selected path will be replaced by the PRGD pattern is specified in TPLC or RPLC. = 1: all 24 channels and the F-bit of the selected path will be replaced by the PRGD pattern. UNF_DET: = 0: which channels of the selected path will be detected by PRGD pattern is specified in TPLC or RPLC. = 1: all 24 channels and the F-bit of the selected path will be detected by PRGD pattern.
209
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RJAT Interrupt Status (010H, 090H, 110H, 190H, 210H, 290H, 310H, 390H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 1 OVRI R X 0 UNDI R X
OVRI: If data are still attempted to write into the FIFO when the FIFO is already full, the overwritten event will occur. = 0: the RJAT FIFO is not overwritten. = 1: the RJAT FIFO is overwritten. This bit is cleared to 0 when it is read. UNDI: If data are still attempted to read from the FIFO when the FIFO is already empty, the under-run event will occur. = 0: the RJAT FIFO is not under-run. = 1: the RJAT FIFO is under-run. This bit is cleared to 0 when it is read. T1 / J1 RJAT Reference Clock Divisor (N1) Control (011H, 091H, 111H, 191H, 211H, 291H, 311H, 391H) Bit No. Bit Name Type Default 7 N1[7] R/W 0 6 N1[6] R/W 0 5 N1[5] R/W 1 4 N1[4] R/W 0 3 N1[3] R/W 1 2 N1[2] R/W 1 1 N1[1] R/W 1 0 N1[0] R/W 1
These bits define a binary number. The (N1[7:0] + 1) is the divisor of the input reference clock, which is the ratio between the frequency of the input reference clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the RJAT. T1 / J1 RJAT Output Clock Divisor (N2) Control (012H, 092H, 112H, 192H, 212H, 292H, 312H, 392H) Bit No. Bit Name Type Default 7 N2[7] R/W 0 6 N2[6] R/W 0 5 N2[5] R/W 1 4 N2[4] R/W 0 3 N2[3] R/W 1 2 N2[2] R/W 1 1 N2[1] R/W 1 0 N2[0] R/W 1
These bits define a binary number. The (N2[7:0] + 1) is the divisor of the output smoothed clock, which is the ratio between the frequency of the output smoothed clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the RJAT.
210
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RJAT Configuration (013H, 093H, 113H, 193H, 213H, 293H, 313H, 393H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 CENT R/W 0 3 UNDE R/W 0 2 OVRE R/W 0 1 Reserved 0 LIMIT R/W 1
CENT: The CENT allows the RJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. = 0: disable the self-center. Data are pass through uncorrupted when the FIFO is empty or full. = 1: enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full. A positive transition in this bit will execute a self-center action immediately. UNDE: This bit decides whether to generate an interrupt when the RJAT FIFO is under-run. = 0: No interrupt is generated when the RJAT FIFO is under-run. = 1: An interrupt on the INT pin is generated when the RJAT FIFO is under-run. OVRE: This bit decides whether to generate an interrupt when the RJAT FIFO is overwritten. = 0: No interrupt is generated when the RJAT FIFO is overwritten. = 1: An interrupt on the INT pin is generated when the RJAT FIFO is overwritten. LIMIT: = 0: disable the limitation of the jitter attenuation. = 1: enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift conditions. T1 / J1 TRSI Timeslot Offset (014H, 094H, 114H, 194H, 214H, 294H, 314H, 394H) Bit No. Bit Name Type Default 7 Reserved 6 TSOFF[6] R/W 0 5 TSOFF[5] R/W 0 4 TSOFF[4] R/W 0 3 TSOFF[3] R/W 0 2 TSOFF[2] R/W 0 1 TSOFF[1] R/W 0 0 TSOFF[0] R/W 0
In T1/J1 Transmit Clock Slave External Signaling mode E1 rate, the content in the TSOFF[6:0] determines the channel offset between the signal on the TSCFS pin and the start of the corresponding frame transmitted on the TSDn & TSSIGn. In T1/J1 Transmit Clock Slave TSFS Enabled mode E1 rate, the content in the TSOFF[6:0] determine the channel offset between the signal on the TSCFS pin and the start of the corresponding frame transmitted on the TSDn. In Transmit Multiplexed mode, the content in the TSOFF[6:0] determine the channel offset between the signal on the MTSCFS pin and the start of the corresponding frame transmitted on the MTSD. Except for the above three modes, the channel offset is disabled. Thus, the TSOFF[6:0] must be logic 0. These bits define a binary number. The offset can be set from 0 to 127 channels.
211
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TRSI Bit Offset (015H, 095H, 115H, 195H, 215H, 295H, 315H, 395H) Bit No. Bit Name Type Default 7 Reserved 6 MTBS R/W 0 5 CMS R/W 0 4 COFF R/W 0 3 Reserved 2 BOFF[2] R/W 0 1 BOFF[1] R/W 0 0 BOFF[0] R/W 0
MTBS: Valid in Transmit Multiplexed mode. = 0: the data of the current channel are taken from the first multiplexed bus (MTSD[1], MTSSIG[1]). = 1: the data of the current channel are taken from the second multiplexed bus (MTSD[2], MTSSIG[2]). CMS: = 0: the clock rate of the TSCCKB/MTSCCKB is the same as that of the backplane. = 1: the clock rate of the TSCCKB/MTSCCKB is twice that of the backplane. The CMS of the eight framers should be set to the same value. COFF: Valid when the CMS (b5, T1/J1-015H) is logic 1. = 0: select the first active edge of the TSCCKB/MTSCCKB to sample / update the data. = 1: select the second active edge of the TSCCKB/MTSCCKB to sample / update the data. In Transmit Clock Multiplexed mode, the COFF of the eight framers should be set to the same value. BOFF[2:0]: In T1/J1 Transmit Clock Slave External Signaling mode E1 rate, the content in the BOFF[2:0] determines the bit offset between the signal on the TSCFS pin and the start of the SF/ESF transmitted on the TSDn & TSSIGn. In T1/J1 Transmit Clock Slave TSFS Enabled mode E1 rate, the content in the BOFF[2:0] determines the bit offset between the signal on the TSCFS pin and the start of the SF/ESF transmitted on the TSDn. In Transmit Multiplexed mode, the content in the BOFF[2:0] determines the bit offset between the signal on the MTSCFS pin and the start of the SF/ESF transmitted on the MTSD & MTSSIG. Except for the above three modes, the bit offset is disabled. Thus, the BOFF[2:0] must be logic 0. These bits define a binary number. Refer to the Functional Description for details.
212
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TJAT Interrupt Status (018H, 098H, 118H, 198H, 218H, 298H, 318H, 398H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 1 OVRI R X 0 UNDI R X
OVRI: If data are still attempted to write into the FIFO when the FIFO is already full, the overwritten event will occur. = 0: the TJAT FIFO is not overwritten. = 1: the TJAT FIFO is overwritten. This bit is cleared to 0 when it is read. UNDI: If data are still attempted to read from the FIFO when the FIFO is already empty, the under-run event will occur. = 0: the TJAT FIFO is not under-run. = 1: the TJAT FIFO is under-run. This bit is cleared to 0 when it is read. T1 / J1 TJAT Reference Clock Divisor (N1) Control (019H, 099H, 119H, 199H, 219H, 299H, 319H, 399H) Bit No. Bit Name Type Default 7 N1[7] R/W 0 6 N1[6] R/W 0 5 N1[5] R/W 1 4 N1[4] R/W 0 3 N1[3] R/W 1 2 N1[2] R/W 1 1 N1[1] R/W 1 0 N1[0] R/W 1
These bits define a binary number. The (N1[7:0] + 1) is the divisor of the input reference clock, which is the ratio between the frequency of the input reference clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the TJAT. T1 / J1 TJAT Output Clock Divisor (N2) Control (01AH, 09AH, 11AH, 19AH, 21AH, 29AH, 31AH, 39AH) Bit No. Bit Name Type Default 7 N2[7] R/W 0 6 N2[6] R/W 0 5 N2[5] R/W 1 4 N2[4] R/W 0 3 N2[3] R/W 1 2 N2[2] R/W 1 1 N2[1] R/W 1 0 N2[0] R/W 1
These bits define a binary number. The (N2[7:0] + 1) is the divisor of the output smoothed clock, which is the ratio between the frequency of the output smoothed clock and the frequency applied to the phase discriminator input. Writing to this register will reset the DPLL in the TJAT.
213
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TJAT Configuration (01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 CENT R/W 0 3 UNDE R/W 0 2 OVRE R/W 0 1 Reserved 0 LIMIT R/W 1
CENT: The CENT allows the TJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. = 0: disable the self-center. Data are pass through uncorrupted when the FIFO is empty or full. = 1: enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full. A positive transition in this bit will execute a self-center action immediately. UNDE: This bit decides whether to generate an interrupt when the TJAT FIFO is under-run. = 0: No interrupt is generated when the TJAT FIFO is under-run. = 1: An interrupt on the INT pin is generated when the TJAT FIFO is under-run. OVRE: This bit decides whether to generate an interrupt when the TJAT FIFO is overwritten. = 0: No interrupt is generated when the TJAT FIFO is overwritten. = 1: An interrupt on the INT pin is generated when the TJAT FIFO is overwritten. LIMIT: = 0: disable the limitation of the jitter attenuation. = 1: enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift conditions. T1 / J1 ELSB Interrupt Enable / Status (01DH, 09DH, 11DH, 19DH, 21DH, 29DH, 31DH, 39DH) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 SLIPE R/W 0 1 SLIPD R X 0 SLIPI R X
SLIPE: = 0: disable the interrupt on the INT pin when a slip occurs. = 1: enable the interrupt on the INT pin when a slip occurs. SLIPD: This bit is applicable when the SLIPI is logic 1. = 0: the latest slip is due to the Elastic Store Buffer being empty; a frame was duplicated. = 1: the latest slip is due to the Elastic Store Buffer being full; a frame was deleted. SLIPI: = 0: no slip occurs. = 1: a slip occurs. This bit is cleared to 0 after the bit is read.
214
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 ELSB Idle Code (01EH, 09EH, 11EH, 19EH, 21EH, 29EH, 31EH, 39EH) Bit No. Bit Name Type Default 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1
These bits set the idle code that will replace the data on the RSDn/MRSD automatically when it is out of SF/ESF sync. D7 is the first bit to be inserted. The writing of the idle code pattern is asynchronous with respect to the output data clock. One channel of idle code data will be corrupted if the register is written to when the framer is out of frame. T1 / J1 FRMP Configuration (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H) Bit No. Bit Name Type Default 7 M2O[1] R/W 0 6 M20[0] R/W 0 5 ESFFA R/W 0 4 ESF R/W 0 3 JYEL R/W 0 2 1 Reserved 0
M20[1:0]: These bits select the SF/ESF frame loss criteria. = 00: 2 of 4 frame alignment bits in error. = 01: 2 of 5 frame alignment bits in error. = 10: 2 of 6 frame alignment bits in error. = 11: Reserved ESFFA: This bit selects the framing algorithm for ESF format. = 0: if four consecutive Frame Alignment Patterns are detected in the F-Bit in the received data stream without the mimic framing pattern, the ESF synchronization is acquired. However, if there are mimic framing patterns in the received data stream, the ESF In-frame is not declared. = 1: when 6 consecutive Frame Alignment Patterns are received error free and the CRC-6 checksum is also error free, the synchronization is acquired. In this condition, the existance of the mimic framing patterns is not considered. ESF: This bit selects the SF or ESF format in the Frame Processor block. = 0: SF format is selected. = 1: ESF format is selected. JYEL: This bit selects the T1 or J1 mode in the Frame Processor block. = 0: T1 mode is selected. = 1: J1 mode is selected.
215
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 FRMP Interrupt Enable (021H, 0A1H, 121H, 1A1H, 221H, 2A1H, 321H, 3A1H) Bit No. Bit Name Type Default 7 Reserved 6 5 COFAE R/W 0 4 FERE R/W 0 3 BEEE R/W 0 2 SFEE R/W 0 1 MFPE R/W 0 0 INFRE R/W 0
COFAE: When the frame alignment pattern has been achieved and the position of the new frame alignment pattern differs from the previous one, this bit decides whether to generate an interrupt or not. = 0: Disables the interrupt when there is a shift on the framing signal position. =1: Enables the interrupt on INT pin when there is a shift on the framing signal position. FERE: = 0: No interrupt is generated when there is a framing bit error. = 1: An interrupt on INT pin is generated when a framing bit error is detected. BEEE: = 0: No interrupt is generated when there is a bit error event. = 1: An interrupt on INT pin is generated when a bit error event occurs. Here, the bit error event is defined as a framing bit error for SF formatted data and a CRC-6 error (the local calculated CRC-6 result is not the same as the received CRC-6 bits) for ESF formatted data. (In SF mode, this bit has the same function as the FERE.) SFEE: The Severe Framing Error is defined as 2 or more framing bit errors during the current super-frame of SF or ESF data. = 0: No interrupt is generated when there is a Severe Framing Error. = 1: An interrupt on INT pin is generated when Severe Framing Error event occurs. MFPE: Mimic Framing Pattern is defined as more than one framing alignment pattern existing simultaneously in the receiving data stream. This bit decides whether to generate an interrupt when Mimic Framing Pattern appears or disappears. = 0: No interrupt is generated when there is a transition of the status of Mimic Framing Pattern. = 1: An interrupt on INT pin is generated when there is a transition (exist to non-exist, or non-exist to exist) of the status of Mimic Framing Pattern. INFRE: This bit decides whether to generate an interrupt when the status of incoming data stream changes from in-frame to out-of-frame or from out-offrame to in-frame. = 0: No interrupt is generated when there is a transition of Frame Synchronize Status. = 1: An interrupt on INT pin is generated when there is a transition of Framing Synchronize Status.
216
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 FRMP Interrupt Status (022H, 0A2H, 122H, 1A2H, 222H, 2A2H, 322H, 3A2H) Bit No. Bit Name Type Default 7 COFAI R 0 6 FERI R 0 5 BEEI R 0 4 SFEI R 0 3 MFPI R 0 2 INFRI R 0 1 MFP R 0 0 INFR R 0
COFAI: = 0: Indicates the framing signal position shift has not occurred. = 1: Indicates the occurrence of framing signal position shift, which means when the frame alignment pattern has been achieved, the position of the new alignment pattern differs from the previous one. This bit is cleared to 0 after it is read. FERI: = 0: Indicates that there is no framing bit error. = 1: Indicates the occurrence of a framing bit error. This bit is cleared to 0 after it is read. BEEI: This bit indicates the occurrence of a bit error event. The bit error event is defined as a framing bit error for SF format or a CRC-6 error (the local calculated CRC-6 result is not the same as the received CRC-6 bits) for ESF format. = 0: Indicates there is no bit error. = 1: Indicates the occurrence of a bit error. (For SF formatted data, this bit has the same function as FERI bit.) This bit is cleared to 0 after it is read SFEI: The Severe Framing Error is defined as 2 or more framing bit errors during the current super-frame of SF or ESF data. = 0: Indicates there is no severe framing error. = 1: Indicates the occurrence of severe framing error. This bit is cleared to 0 after it is read. MFPI: This bit indicates the transition of the status of the current mimic framing pattern. = 0: When the status of current mimic framing pattern is not changed. = 1: When there is a transition (exist to non-exist, or non-exist to exist) of the status of mimic framing pattern. This bit is cleared to 0 after it is read. INFRI: This bit indicates the transition of frame synchronization status. = 0: When the frame synchronization status is not changed. = 1: When the frame synchronization status of the receiving data stream changes from in-frame to out-of-frame or from out-of-frame to in-frame. MFP: This bit reflects the current status of mimic framing pattern. = 0: Indicates that the mimic framing pattern does not exist. = 1: Indicates the presence of more than one framing alignment patterns in the receiving data stream. Read operation will not change the status of this bit. INFR: This bit reflects the current status of frame synchronization. = 0: The received data stream is out-of-frame. = 1: The received data stream is in-frame. Read operation will not change the status of this bit.
217
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 Clock Monitor (027H, 0A7H, 127H, 1A7H, 227H, 2A7H, 327H, 3A7H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 XCK R X 3 TSCCKB R X 2 TSCCKA R X 1 RSCCK R X 0 LRCK R X
This register provides monitoring on the IDT82V2108 clocks. When a monitored clock signal makes a low to high transition, the corresponding bit in this register is set to 1, and this bit remains to be 1 until this register is read. After a read operation on this register, all the bits in this register will be cleared to 0. A lack of transitions of the monitored clock will be indicated by 0 in the corresponding bit, which means that the clock fails. This register should be read periodically to detect clock failures. XCK: = 0: after the bit is read. = 1: a low to high transition occurs on the XCK. TSCCKB: = 0: after the bit is read. = 1: a low to high transition occurs on the TSCCKB. TSCCKA: = 0: after the bit is read. = 1: a low to high transition occurs on the TSCCKA. RSCCK: = 0: after the bit is read. = 1: a low to high transition occurs on the RSCCK. LRCK: = 0: after the bit is read. = 1: a low to high transition occurs on the LRCK.
218
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RBOM Enable (02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 IDLE R/W 0 1 AVC R/W 0 0 BOCE R/W 0
IDLE: = 0: disable the interrupt on the INT pin when there is a transition from BOM to non-BOM in the received data stream. = 1: enable the interrupt on the INT pin when there is a transition from BOM to non-BOM in the received data stream. AVC: This bit selects the validation criteria used to acknowledge the Bit Oriented Message (BOM) in the received data stream, or to acknowledge the Yellow signal in T1/J1 ESF format. = 0: the BOM or the Yellow signal is acknowledged when the pattern is matched and the received code is identical 8 out of 10 times. = 1: the BOM or the Yellow signal is acknowledged when the pattern is matched and the received code is identical 4 out of 5 times. BOCE: = 0: disable the interrupt on the INT pin when a valid BOM code is detected in the received data stream. = 1: enable the interrupt on the INT pin when a valid BOM code is detected in the received data stream. T1 / J1 RBOM Code Status (02BH, 0ABH, 12BH, 1ABH, 22BH, 2ABH, 32BH, 3ABH) Bit No. Bit Name Type Default 7 IDLEI R 0 6 BOCI R 0 5 BOC[5] R 1 4 BOC[4] R 1 3 BOC[3] R 1 2 BOC[2] R 1 1 BOC[1] R 1 0 BOC[0] R 1
IDLEI: = 0: no transition from Bit Oriented Message (BOM) to non-BOM in the received data stream. = 1: a transition from BOM to non-BOM in the received data stream. This bit is cleared to 0 after the register is read. BOCI: = 0: no Bit Oriented Message (BOM) is detected. = 1: BOM is detected in the received data stream. This bit is cleared to 0 after the register is read. BOC[5:0]: These bits directly reflect the content of the Bit Oriented Message (BOM) in the received data stream. All ones in the BOC[5:0] mean there is no BOM received. The BOC[5] corresponds to the MSB of the code while the BOC[0] corresponds to the LSB.
219
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 ALMD Configuration (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH) Bit No. Bit Name Type Default 7 Reserved 6 5 J1_YEL R/W 0 4 ESF R/W 0 3 2 Reserved 1 0
J1_YEL: This bit selects the T1 or J1 mode in the Alarm Detector block. = 0: T1 mode is selected in the ALMD block. = 1: J1 mode is selected in the ALMD block. ESF: This bit selects the SF or ESF format in the Alarm Detector block. = 0: SF format is selected. = 1: ESF format is selected. T1 / J1 ALMD Interrupt Enable (02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 FASTD R/W 0 3 Reserved 2 YELE R/W 0 1 REDE R/W 0 0 AISE R/W 0
FASTD: = 0: the RED Alarm is cleared when the out of SF/ESF sync event has been absent for 16.6sec (500ms); the AIS Alarm is cleared when the AIS signal has been absent for 16.8sec (500ms). = 1: the RED Alarm is cleared when the out of SF/ESF sync event has been absent for 120ms; the AIS Alarm is cleared when the AIS signal has been absent for 180ms. YELE: = 0: disable the interrupt on the INT pin when the YELI (b5, T1/J1-02EH) is logic one. = 1: enable the interrupt on the INT pin when the YELI (b5, T1/J1-02EH) is logic one. REDE: = 0: disable the interrupt on the INT pin when the REDI (b4, T1/J1-02EH) is logic one. = 1: enable the interrupt on the INT pin when the REDI (b4, T1/J1-02EH) is logic one. AISE: = 0: disable the interrupt on the INT pin when the AISI (b3, T1/J1-02EH) is logic one. = 1: enable the interrupt on the INT pin when the AISI (b3, T1/J1-02EH) is logic one.
220
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 ALMD Interrupt Status (02EH, 0AEH, 12EH, 1AEH, 22EH, 2AEH, 32EH, 3AEH) Bit No. Bit Name Type Default 7 Reserved 6 5 YELI R 0 4 REDI R 0 3 AISI R 0 2 YEL R 0 1 RED R 0 0 AIS R 0
YELI: = 0: there is no transition (from 1 to 0 or from 0 to 1) on the YEL (b2, T1/J1-02EH). = 1: there is a transition (from 1 to 0 or from 0 to 1) on the YEL (b2, T1/J1-02EH). This bit is clear to 0 after the register is read. REDI: = 0: there is no transition (from 1 to 0 or from 0 to 1) on the RED (b1, T1/J1-02EH). = 1: there is a transition (from 1 to 0 or from 0 to 1) on the RED (b1, T1/J1-02EH). This bit is clear to 0 after the register is read. AISI: = 0: there is no transition (from 1 to 0 or from 0 to 1) on the AIS (b0, T1/J1-02EH). = 1: there is a transition (from 1 to 0 or from 0 to 1) on the AIS (b0, T1/J1-02EH). This bit is clear to 0 after the register is read. YEL: = 0: the Yellow signal has been absent for 425ms (50ms). = 1: the Yellow signal has been present for 425ms (50ms). RED: = 0: the REDD (b2, T1/J1-02FH) has been logic 0 for 16.6sec (500ms), or for 120ms if the FASTD (b4, T1/J1-02DH) is set. = 1: the REDD (b2, T1/J1-02FH) has been logic 1 for 2.55sec (40ms). AIS: = 0: the AIS signal has been absent for 16.8sec (500ms), or for 180ms if the FASTD (b4, T1/J1-02DH) is set. = 1: the AIS signal has been present for 1.5sec (100ms).
221
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 ALMD Alarm Detection Status (02FH, 0AFH, 12FH, 1AFH, 22FH, 2AFH, 32FH, 3AFH) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 REDD R X 1 YELD R X 0 AISD R X
REDD: = 0: no out of SF/ESF sync event has occurred in the latest 40ms period. = 1: one or more out of SF/ESF sync events have occurred in the latest 40ms period. YELD: = 0: In SF format, the Yellow signal is absent during the latest 40ms period; in ESF format, the Yellow signal is absent during the latest 4ms period. = 1: In SF format, the Yellow signal is present during the latest 40ms period; in ESF format, when the AVC (b1, T1/J1-02AH) is 0, the Yellow signal is present during the latest 40ms period, when the AVC (b1, T1/J1-02AH) is 1, the Yellow signal is present during the latest 20ms period. The Yellow signal is acknowledged differently in each format: - In T1 SF format: The Yellow signal occupies the 2nd bit of each channel. When the bit is logic 1 for 16 or fewer times during the 40ms period, the Yellow signal is present. - In J1 SF format: The Yellow signal occupies the F-bit of the 12th frame. However, when the bit is logic 0 for 2 or fewer times during the 40ms period, the Yellow signal is present. - In T1/J1 ESF format: The Yellow signal occupies the DL of the F-bit (refer to Table-4). The pattern is `FF00' in T1 mode and `FFFF' in J1 mode. When the AVC (b1, T1/J1-02AH) is logic 0, the Yellow signal is acknowledged if the pattern is matched in 8 out of 10 successive DL. When the AVC (b1, T1/J1-02AH) is logic 1, the Yellow signal is acknowledged if the pattern is matched in 4 out of 5 successive DL. AISD: = 0: the AIS signal is absent during the latest 60ms period. = 1: the AIS signal is present during the latest 60ms period. The AIS signal is acknowledged when the received data are out of SF/ESF synchronization for 60ms and the received logic 0 is less than 127 times in the same period.
222
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TPLC Configuration (030H, 0B0H, 130H, 1B0H, 230H, 2B0H, 330H, 3B0H) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 PCCE R/W 0
PCCE: = 0: the per-channel functions in TPLC are disabled. = 1: the per-channel functions in TPLC are enabled. T1 / J1 TPLC P Access Status (031H, 0B1H, 131H, 1B1H, 231H, 2B1H, 331H, 3B1H) Bit No. Bit Name Type Default 7 BUSY R 0 6 5 4 3 Reserved 2 1 0
BUSY: = 0: no reading or writing operation on the indirect registers. = 1: an internal indirect register is being accessed, any new operation on the internal indirect register is not allowed. This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 650ns. No more operations to the indirect registers could be done until this bit is cleared. T1 / J1 TPLC Channel Indirect Address / Control (032H, 0B2H, 132H, 1B2H, 232H, 2B2H, 332H, 3B2H) Bit No. Bit Name Type Default 7 R/WB R/W 0 6 A6 R/W 0 5 A5 R/W 0 4 A4 R/W 0 3 A3 R/W 0 2 A2 R/W 0 1 A1 R/W 0 0 A0 R/W 0
Writing to this register with a valid address and R/WB bit initiates an internal operation cycle to the indirect registers. R/WB: = 0: write the data to the specified indirect register. = 1: read the data from the specified indirect register. A[6:0]: Specify the address of the indirect registers (from 01H to 48H) for the microprocessor access.
223
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TPLC Channel Indirect Data Buffer (033H, 0B3H, 133H, 1B3H, 233H, 2B3H, 333H, 3B3H) Bit No. Bit Name Type Default 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
This register hold the value which will be read from or write into the indirect registers (from 01H to 48H). If data are to be written to the indirect registers, the byte to be written must be written into this register before the target indirect register's address and R/WB=0 is written into the Address/ Control register, initiating the access. If data are to be read from the indirect registers, only the target indirect register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 490 ns, this register will contain the requested data byte. TPLC Indirect Registers Map Per-Channel Control for Channel 1 ~ 24 IDLE Code Byte for Channel 1 ~ 24 Signaling Control Byte for Channel 1 ~ 24
01H ~ 18H 19H ~ 30H 31H ~ 48H
224
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TPLC Per-Channel Control Registers (TPLC Indirect Registers 01H - 18H) Bit No. Bit Name Type Default 7 INVERT R/W X 6 IDLE_DS0 R/W X 5 DMW R/W X 4 SIGNINV R/W X 3 TEST R/W X 2 LOOP R/W X 1 ZCS[1] R/W X 0 ZCS[0] R/W X
INVERT: This bit, together with the SIGNINV (b4, T1/J1-TPLC-indirect register - 01~18H), determines the bit inversion of the corresponding channel when input from the TSDn/MTSD pin. INVERT SIGNINV Bit Inversion 0 0 No bit inversion 0 1 Invert the MSB of the corresponding channel 1 0 Invert all the bits of the corresponding channel 1 1 Invert all the bits except the MSB of the corresponding channel IDLE_DS0: = 0: disable the data in the corresponding channel to be replaced by the data set in the IDLE[7:0] when input from the TSDn/MTSD pin. = 1: enable the data in the corresponding channel to be replaced by the data set in the IDLE[7:0] when input from the TSDn/MTSD pin. DMW: = 0: disable the data in the corresponding channel to be replaced with a digital milliwatt pattern when input from the TSDn/MTSD pin. = 1: enable the data in the corresponding channel to be replaced with a digital milliwatt pattern when input from the TSDn/MTSD pin. SIGNINV: Refer to the INVERT (b7, T1/J1-TPLC-indirect register - 01~18H). TEST: = 0: disable the data in the corresponding channel to be tested by PRGD. = 1: enable the data in the corresponding channel to be extracted to PRGD for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 1), or enable the test pattern from PRGD to replace the data in the corresponding channel for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 0). All the timeslots that are extracted to the PRGD are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all timeslots set to be replaced with PRGD test pattern data are concatenated replaced by the PRBS. LOOP: = 0: disable the payload loopback. = 1: enable the payload loopback. When the Receive Clock Master modes are enabled, the Elastic Store is used to align the receive line data to the data to be transmitted. When Receive Clock Slave modes are enabled, the Elastic Store is unavailable to facilitate the payload loopbacks, and loopback functionality is provided only when the transmit path is also in Transmit Clock Slave mode, and the received clock and the clock to be transmitted and Common Frame Pulse are identical (RSCCK = TSCCKB, RSCFS = TSCFS). ZCS[1:0]: ZCS[1:0] 00 01 10 11
Per-Channel Zero Code Suppression No zero code suppression. Every bit 8 in the corresponding channel is forced to be logic one. GTE Zero Code Suppression - Every bit 8 (or bit 7 in signaling frames) is forced to be logic one when the bits in the corresponding channel are all zeros. Bell Zero Code Suppression - Every bit 7 is forced to be logic one when the bits in the corresponding channel are all zeros.
The priority of the TPLC operation on the TSDn/MTSD pin from high to low is: Extract data to PRGD for test; Zero Code Suppression; Payload loopback; Replace the data with the milliwatt pattern; Replace the data with the pattern generated in the PRGD; Replace the data with the value in the IDLE[7:0]; Invert the bit.
225
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TPLC IDLE Code Byte Registers (TPLC Indirect Registers 19H - 30H) Bit No. Bit Name Type Default 7 IDLE7 R/W X 6 IDLE6 R/W X 5 IDLE5 R/W X 4 IDLE4 R/W X 3 IDLE3 R/W X 2 IDLE2 R/W X 1 IDLE1 R/W X 0 IDLE0 R/W X
They contain the data that will replace the data input from the TSDn/MTSD pin when the corresponding IDLE_DS0 is logic 1. IDLE7 is the MSB. T1 / J1 TPLC Signaling Control Byte Registers (TPLC Indirect Registers 31H - 48H) Bit No. Bit Name Type Default 7 SIGC0 R/W X 6 SIGC1 R/W X 5 Reserved 4 3 A R/W X 2 B R/W X 1 C R/W X 0 D R/W X
SIGC0: This bit is valid when the corresponding SIGC1 is logic 1. = 0: use the data input from the TSSIGn/MTSSIG pin as the signaling. = 1: use the data in the A, B, C, D as the signaling. SIGC1: = 0: disable replacing the signaling bit with the data input from the TSSIGn/MTSSIG pin or the data in the A, B, C, D. = 1: enable replacing the signaling bit with the data input from the TSSIGn/MTSSIG pin or the data in the A, B, C, D. A, B, C, D: They contain the data that can be used as signaling when the corresponding SIGC0 is logic 1. They are in the least significant nibble.
226
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 THDLC #1, #2 Configuration (034H, 0B4H, 134H, 1B4H, 234H, 2B4H, 334H, 3B4H) Bit No. Bit Name Type Default 7 FLGSHARE R/W 1 6 FIFOCLR R/W 0 5 Reserved 4 3 EOM R/W 0 2 ABT R/W 0 1 CRC R/W 1 0 EN R/W 0
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/ J1-00DH). FLGSHARE: = 0: the closing flag of the current HDLC and the opening flag of the next HDLC are separate. = 1: the closing flag of the current HDLC and the opening flag of the next HDLC are shared. FIFOCLR: = 0: normal operation. = 1: clear the FIFO. EOM: = 0: normal operation. = 1: a positive transition of this bit starts a packet transmission. Then if the CRC(b1, E1-050H) is set, the 16-bit FCS word is appended to the last data byte transmitted. ABT: = 0: normal operation. = 1: transmit the 7F abort sequence after the current setting in the Transmit Data register is transmitted, so that the FIFO is cleared and all data in the FIFO will be lost. Aborts are continuously sent and the FIFO is held in reset until this bit is reset to a logic 0. At least one Abort sequence will be sent when the ABT transitions from logic 0 to logic 1. CRC: = 0: do not append the CRC-16 frame check sequences (FCS) to the end of the HDLC data. = 1: append the FCS to the end of the HDLC data EN: = 0: disable the operation of the THDLC block and transmit all ones on the assigned data link. = 1: enable the operation of the THDLC block and flag sequences are sent until data are written into the THDLC Transmit Data register and the EOM is set to logic 1.
227
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 THDLC #1, #2 Upper Transmit Threshold (035H, 0B5H, 135H, 1B5H, 235H, 2B5H, 335H, 3B5H) Bit No. Bit Name Type Default 7 Reserved 6 UTHR[6] R/W 1 5 UTHR[5] R/W 0 4 UTHR[4] R/W 0 3 UTHR[3] R/W 0 2 UTHR[2] R/W 0 1 UTHR[1] R/W 0 0 UTHR[0] R/W 0
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/ J1-00DH). UTHR[6:0]: These bits define the upper fill level of the FIFO. Once the fill level exceeds the UTHR[6:0] value, the data stored in the FIFO will start to transmit. The transmission will not stop until the last complete packet is transmitted and the THDLC FIFO fill level is below UTHR[6:0] + 1. It should be greater than the value of the LINT[6:0] unless both are equal to 00H. T1 / J1 THDLC #1, #2 Lower Interrupt Threshold (036H, 0B6H, 136H, 1B6H, 236H, 2B6H, 336H, 3B6H) Bit No. Bit Name Type Default 7 Reserved 6 LINT[6] R/W 0 5 LINT[5] R/W 0 4 LINT[4] R/W 0 3 LINT[3] R/W 0 2 LINT[2] R/W 1 1 LINT[1] R/W 1 0 LINT[0] R/W 1
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/ J1-00DH). LINT[6:0]: These bits define the fill level of the FIFO that can cause an interrupt. That is, when the fill level of the FIFO is below the LINT[6:0], an interrupt will be generated. It should be less than the value of the UTHR[6:0] unless both are equal to 00H.
228
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 THDLC #1, #2 Interrupt Enable (037H, 0B7H, 137H, 1B7H, 237H, 2B7H, 337H, 3B7H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 FULLE R/W 0 2 OVRE R/W 0 1 UDRE R/W 0 0 LFILLE R/W 0
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/ J1-00DH). FULLE: = 0: disable the interrupt on the INT pin when the FULLI (b3, T1/J1-038H) is logic 1. = 1: enable the interrupt on the INT pin when the FULLI (b3, T1/J1-038H) is logic 1. OVRE: = 0: disable the interrupt on the INT pin when the OVRI (b2, T1/J1-038H) is logic 1. = 1: enable the interrupt on the INT pin when the OVRI (b2, T1/J1-038H) is logic 1. UDRE: = 0: disable the interrupt on the INT pin when the UDRI (b1, T1/J1-038H) is logic 1. = 1: enable the interrupt on the INT pin when the UDRI (b1, T1/J1-038H) is logic 1. LFILLE: = 0: disable the interrupt on the INT pin when the LFILLI (b0, T1/J1-038H) is logic 1. = 1: enable the interrupt on the INT pin when the LFILLI (b0, T1/J1-038H) is logic 1.
229
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 THDLC #1, #2 Interrupt Status / UDR Clear (038H, 0B8H, 138H, 1B8H, 238H, 2B8H, 338H, 3B8H) Bit No. Bit Name Type Default 7 Reserved 6 FULL R X 5 BLFILL R X 4 Reserved 3 FULLI R X 2 OVRI R X 1 UDRI R X 0 LFILLI R X
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/ J1-00DH). FULL: = 0: the THDLC FIFO is not full. = 1: the THDLC FIFO is full (128 bits). BLFILL: = 0: the data in the THDLC FIFO are not below the value of the LINT[6:0] (b6~0, T1/J1-036H). = 1: the data in the THDLC FIFO are empty or below the value of the LINT[6:0] (b6~0, T1/J1-036H). FULLI: = 0: there is no transition (from 0 to 1) on the FULL. = 1: there is a transition (from 0 to 1) on the FULL. This bit is clear to 0 after the bit is read. OVRI: The Over-Written is that the THDLC FIFO was already full when another data byte was written to the THDLC Transmit Data register. = 0: the THDLC FIFO is not overwritten. = 1: the THDLC FIFO is overwritten (more than 128 bits). This bit is clear to 0 after the bit is read. UDRI: The Under-Run is that the THDLC was in the process of transmitting a packet when it ran out of data to be transmitted. = 0: the THDLC FIFO is not under-run. = 1: the THDLC FIFO is under-run. This bit is clear to 0 after the bit is read. LFILLI: = 0: there is no transition (from 0 to 1) on the BLFILL. = 1: there is a transition (from 0 to 1) on the BLFILL. This bit is clear to 0 after the bit is read.
230
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 THDLC #1, #2 Transmit Data (039H, 0B9H, 139H, 1B9H, 239H, 2B9H, 339H, 3B9H) Bit No. Bit Name Type Default 7 TD[7] R/W X 6 TD[6] R/W X 5 TD[5] R/W X 4 TD[4] R/W X 3 TD[3] R/W X 2 TD[2] R/W X 1 TD[1] R/W X 0 TD[0] R/W X
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/ J1-00DH). The content is the data to be transmitted. It is serially transmitted (TD[0] is the first). T1 / J1 IBCD Configuration (03CH, 0BCH, 13CH, 1BCH, 23CH, 2BCH, 33CH, 3BCH) Bit No. Bit Name Type Default 7 Reserved 6 5 4 IBCD_ERR[1] IBCD_ERR[0] R/W R/W 0 0 3 DSEL1 R/W 0 2 DSEL0 R/W 0 1 ASEL1 R/W 0 0 ASEL0 R/W 0
IBCD_ERR[1:0]: The IBCD_ERR[1:0] sets the error tolerance in the received activate/deactivate code within 39.8ms: IBCD_ERR[1:0] Error Tolerance 00 0 bit 01 200 bits 10 20 bits 11 2 bits DSEL[1:0]: The DSEL[1:0] define the length of the received loopback deactivate code, meanwhile, it define the valid code in the DACT[7:0] (b7~0, T1/J103FH): DSEL[1:0] Deactivate Code Length & Valid Code In the DACT[7:0] 00 5-bit length & the code in the DACT[7:3] is valid 01 6-bit or 3-bit length & the code in the DACT[7:2] is valid 10 7-bit length & the code in the DACT[7:1] is valid 11 8-bit or 4-bit length & the code in the DACT[7:0] is valid ASEL[1:0]: The ASEL[1:0] define the length of the received loopback activate code, meanwhile, it define the valid code in the ACT[7:0] (b7~0, T1/J1-03EH): ASEL[1:0] Activate Code Length & Valid Code In the ACT[7:0] 00 5-bit length & the code in the ACT[7:3] is valid 01 6-bit or 3-bit length & the code in the ACT[7:2] is valid 10 7-bit length & the code in the ACT[7:1] is valid 11 8-bit or 4-bit length & the code in the ACT[7:0] is valid
231
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 IBCD Interrupt Enable / Status (03DH, 0BDH, 13DH, 1BDH, 23DH, 2BDH, 33DH, 3BDH) Bit No. Bit Name Type Default 7 LBACP R 0 6 LBDCP R 0 5 LBAE R/W 0 4 LBDE R/W 0 3 LBAI R 0 2 LBDI R 0 1 LBA R 0 0 LBD R 0
LBACP: = 0: no loopback activate code is present for 39.8ms. = 1: the loopback activate code is present for 39.8ms. LBDCP: = 0: no loopback deactivate code is present for 39.8ms. = 1: the loopback deactivate code is present for 39.8ms. LBAE: = 0: disable the interrupt on the INT pin when the loopback activate code status changes (i.e., the LBAI is logic one). = 1: enable the interrupt on the INT pin when the loopback activate code status changes (i.e., the LBAI is logic one). LBDE: = 0: disable the interrupt on the INT pin when the loopback deactivate code status changes (i.e., the LBDI is logic one). = 1: enable the interrupt on the INT pin when the loopback deactivate code status changes (i.e., the LBDI is logic one). LBAI: = 0: the loopback activate code status does not change. = 1: the loopback activate code status changes (i.e., there is a transition from 0 to 1 or from 1 to 0 on the LBA). This bit is cleared to 0 after the register is read. LBDI: = 0: the loopback deactivate code status does not change. = 1: the loopback deactivate code status changes (i.e., there is a transition from 0 to 1 or from 1 to 0 on the LBD). This bit is cleared to 0 after the register is read. LBA: = 0: no loopback activate code is present for 5.1s. = 1: the loopback activate code is present for 5.1s. LBD: = 0: no loopback deactivate code is present for 5.1s. = 1: the loopback deactivate code is present for 5.1s.
232
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 IBCD Activate Code (03EH, 0BEH, 13EH, 1BEH, 23EH, 2BEH, 33EH, 3BEH) Bit No. Bit Name Type Default 7 ACT7 R/W 0 6 ACT6 R/W 0 5 ACT5 R/W 0 4 ACT4 R/W 0 3 ACT3 R/W 0 2 ACT2 R/W 0 1 ACT1 R/W 0 0 ACT0 R/W 0
The ACT[7:X] defines the content of the activate code. `X' is 3, 2, 1 or 0 and depends on the length defined by the ASEL[1:0] (b1~0, T1/J1-03CH). The unused bits should be ignored. The ACT[7] is the MSB and compares with the first received code bit. T1 / J1 IBCD Deactivate Code (03FH, 0BFH, 13FH, 1BFH, 23FH, 2BFH, 33FH, 3BFH) Bit No. Bit Name Type Default 7 DACT7 R/W 0 6 DACT6 R/W 0 5 ADCT5 R/W 0 4 DACT4 R/W 0 3 DACT3 R/W 0 2 DACT2 R/W 0 1 DACT1 R/W 0 0 DACT0 R/W 0
The DACT[7:X] defines the content of the deactivate code. `X' is 3, 2, 1 or 0 and depends on the length defined by the DSEL[1:0] (b3~2, T1/J103CH). The unused bits should be ignored. The DACT[7] is the MSB and compares with the first received code bit. T1 / J1 RCRB Configuration (COSS = 0) (040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H) Bit No. Bit Name Type Default 7 Reserved 6 COSS R/W 0 5 SIGE R/W 0 4 Reserved 3 2 ESF R/W 0 1 Reserved 0 PCCE R/W 0
COSS: = 0: allow the RCRB registers to access the indirect registers. = 1: allow the RCRB registers to reflect the change of the signaling of its corresponding channel. SIGE: = 0: disable generation of an interrupt on the INT pin when there is signaling change in any one of the 24 channels. = 1: enable generation of an interrupt on the INT pin when there is signaling change in any one of the 24 channels. ESF: This bit selects the SF or ESF format in the Receive CAS/RBS Buffer block. = 0: SF format is selected. = 1: ESF format is selected. PCCE: = 0: the per-channel functions in RCRB are disabled. = 1: the per-channel functions in RCRB are enabled.
233
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RCRB Channel Indirect Status (COSS = 0) (041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H) Bit No. Bit Name Type Default 7 BUSY R 0 6 5 4 3 Reserved 2 1 0
BUSY: = 0: no reading or writing operation on the indirect registers is occurring. = 1: an internal indirect register is being accessed, any new operation on the internal indirect register is not allowed. This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 650ns. No more operations to the indirect registers could be done until this bit is cleared. T1 / J1 RCRB Channel Indirect Address / Control (COSS = 0) (042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H) Bit No. Bit Name Type Default 7 R/WB R/W 0 6 A6 R/W 0 5 A5 R/W 0 4 A4 R/W 0 3 A3 R/W 0 2 A2 R/W 0 1 A1 R/W 0 0 A0 R/W 0
R/WB: = 0: write the data to the specified indirect register. = 1: read the data from the specified indirect register. A[6:0]: Specifies the address of the indirect registers (from 20H to 57H) for the microprocessor access. T1 / J1 RCRB Channel Indirect Data Buffer (COSS = 0) (043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H) Bit No. Bit Name Type Default 7 D7 R/W X 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X
This register holds the value which will be read from or written to the indirect registers (from 20H to 57H). If data are to be written to the indirect registers, the byte to be written must be written into this register before the target indirect register's address and R/WB=0 is written into the Address/ Control register, initiating the access. If data are to be read from the indirect registers, only the target indirect register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte.
234
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RCRB Configuration (COSS = 1) (040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H) Bit No. Bit Name Type Default 7 Reserved 6 COSS R/W 0 5 4 3 Reserved 2 1 0
COSS: = 0: allow the RCRB registers to access the indirect registers. = 1: allow the RCRB registers to reflect the change of the signaling of its corresponding channel. T1 / J1 RCRB Signaling State Change Channels 17-24 (COSS = 1) (041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H) Bit No. Bit Name Type Default 7 COSS[24] R X 6 COSS[23] R X 5 COSS[22] R X 4 COSS[21] R X 3 COSS[20] R X 2 COSS[19] R X 1 COSS[18] R X 0 COSS[17] R X
COSSn: = 0: the signaling in its corresponding channel is not changed. = 1: the signaling in its corresponding channel is changed. These bits are cleared to 0 after the register is read. COSS[24:17] correspond to channels 24 to 17. T1 / J1 RCRB Signaling State Change Channels 9-16 (COSS = 1) (042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H) Bit No. Bit Name Type Default 7 COSS[16] R X 6 COSS[15] R X 5 COSS[14] R X 4 COSS[13] R X 3 COSS[12] R X 2 COSS[11] R X 1 COSS[10] R X 0 COSS[9] R X
COSSn: = 0: the signaling in its corresponding channel is not changed. = 1: the signaling in its corresponding channel is changed. These bits are cleared to 0 after the register is read. COSS[16:9] correspond to channels 16 to 9. T1 / J1 RCRB Signaling State Change Channels 1-8 (COSS = 1) (043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H) Bit No. Bit Name Type Default 7 COSS[8] R X 6 COSS[7] R X 5 COSS[6] R X 4 COSS[5] R X 3 COSS[4] R X 2 COSS[3] R X 1 COSS[2] R X 0 COSS[1] R X
COSSn: = 0: the signaling in its corresponding channel is not changed. = 1: the signaling in its corresponding channel is changed. These bits are cleared to 0 after the register is read. COSS[8:1] correspond to channels 8 to 1.
235
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
01H ~ 18H / 21H ~ 38H 19H ~ 20H, 39H ~ 40H 41H ~ 58H
RCRB Indirect Registers Map Channel Signaling Data Register for Channel 1 ~ 24 Per-Channel Configuration Register for Channel 1 ~ 24
T1 / J1 RCRB Channel Signaling Data Registers (COSS = 0) (RCRB Indirect Registers 01H ~ 18H / 21H - 38H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 A R X 2 B R X 1 C R X 0 D R X
A, B, C, D: They contain the signaling of the corresponding channel. There is a maximum 2 ms delay between the transition of the COSS[n] bit (T1/J1-041H & T1/J1-042H & T1/J1-043H) and the updating of the A, B, C, D code in the corresponding indirect registers 21H ~ 38H. To avoid this 2ms delay, users can read the corresponding b3~0 in the indirect registers 01H ~ 18H first. If the value of these four bits are different from the previous A, B, C, D code, then the content of b3~0 in the 01H ~ 18H is the updated A, B, C, D code. If the conternt of the four bits is the same as the previous A, B, C, D code, then users should read the b3~0 in the 21H ~ 38H to get the updated A, B, C, D code. In SF format, the C and D are the repetition of the A and B respectively. T1 / J1 RCRB Per-Channel Configuration Registers (COSS = 0) (RCRB Indirect Registers 41H - 58H) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 DEB R/W X
DEB: = 0: disable signaling debounce. = 1: enable signaling debounce (valid only if the PCCE is logic 1). That is, the signaling is acknowledged only when 2 consecutive signaling bits of a channel are the same.
236
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 FRMG Configuration (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H) Bit No. Bit Name Type Default 7 MTRK R/W 0 6 J1_CRC R/W 0 5 J1_YEL R/W 0 4 ESF R/W 0 3 Reserved 2 1 GZCS[1] R/W 0 0 GZCS[0] R/W 0
MTRK: Valid when the PCCE (b0, T1/J1-030H) is logic 1. = 0: normal operation. = 1: replace the data on all channels with the data set in the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers-19~30H); replace the signaling on all channels with the data on the TSSIGn/MTSSIG pin or the data in the A, B, C, D (b3~0, T1/J1-TPLC-indirect registers-31~48H) according to the setting in the SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers-31~48H). J1_CRC: This bit selects the T1 or J1 CRC-6 algorithm when the ESF (b4, T1/J1-044H) is 1. = 0: the CRC-6 algorithm meets T1 standard. = 1: the CRC-6 algorithm meets J1 standard. J1_YEL: This bit selects the T1 or J1 Yellow alarm pattern to be transmitted. = 0: the Yellow alarm transition meets T1 standard. = 1: the Yellow alarm transition meets J1 standard. The Yellow alarm pattern is: - In T1 SF format: Transmit the logic 0 on the 2nd bit of each channel. - In T1 ESF format: Transmit the `FF00' on each FDL link. - In J1 SF format: Transmit the logic 1 on the 12th F-bit. - In J1 ESF format: Transmit the `FFFF' on each FDL link. The SF or ESF format is selected by the ESF (b4, T1/J1-044H). ESF: This bit selects the SF or ESF format in the Frame Generator block. = 0: the SF format is selected. = 1: the ESF format is selected. GZCS[1:0]: These bits select the Zero Code Suppression format to be used. They are logically ORed with the ZCS[1:0] (b1~0, T1/J1-TPLC-indirect registers01~18H). GZCS[1:0] Zero Code Suppression 00 No zero code suppression. 01 GTE Zero Code Suppression - Every bit 8 (or bit 7 in signaling frames) is forced to be logic one when the bits in a channel are all zeros. 10 Reserved. 11 Bell Zero Code Suppression - Every bit 7 is forced to be logic one when the bits in a channel are all zeros.
237
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 FRMG Alarm Transmit (045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 1 XYEL R/W 0 0 Reserved
XYEL: = 0: disable generating Yellow alarm manually. = 1: enable generating Yellow alarm manually. T1 / J1 IBCG Control (046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H) Bit No. Bit Name Type Default 7 EN R/W 0 6 UF R/W 0 5 4 Reserved 3 2 1 CL1 R/W 0 0 CL0 R/W 0
EN: = 0: disable transmiting the inband loopback code. = 1: enable transmiting the inband loopback code. UF: = 0: the Frame Generator block operates normally. It transmits the inband loopback code in framed mode, that is, only the 192 bits are replaced with the inband loopback while the F-bit is occupied by Frame Alignment Pattern, DL or CRC-6. = 1: disable the Frame Generator block, that is, disable to form the SF/ESF frame. It transmits the inband loopback code in un-framed mode, that is, all 193 bits are replaced with the inband loopback code. CL[1:0]: The CL[1:0] define the length of the loopback code to be transmitted, meanwhile, they define the valid code in the IBC[7:0] (b7~0, T1/J1-047H): CL[1:0] Loopback Code Length & valid code in the IBC[7:0] 00 5-bit length & the code in the IBC[7:3] is valid 01 6-bit or 3-bit length & the code in the IBC[7:2] is valid 10 7-bit length & the code in the IBC[7:1] is valid 11 8-bit or 4-bit length & the code in the IBC[7:0] is valid
238
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 IBCG Loopback Code (047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H) Bit No. Bit Name Type Default 7 IBC7 R/W X 6 IBC6 R/W X 5 IBC5 R/W X 4 IBC4 R/W X 3 IBC3 R/W X 2 IBC2 R/W X 1 IBC1 R/W X 0 IBC0 R/W X
The IBC[7:X] defines the content of the inband loopback code. `X' is one of 3 to 0 which is depending on the length defined by the CL[1:0] (b1~0, T1/J1-046H). The IBC[7] is the MSB. T1 / J1 PMON Interrupt Enable / Status (049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 INTE R/W 0 1 XFER R 0 0 OVR R 0
INTE: = 0: disabled the interrupt on the INT pin when the counter data has been transferred into the Error Count registers. = 1: enabled the interrupt on the INT pin when the counter data has been transferred into the Error Count registers. XFER: = 0: indicate that the counter data has not been transferred to the Error Count registers. = 1: indicate that the counter data has been transferred to the Error Count registers. This bit is clear to 0 after the bit is read. OVR: = 0: indicate that no overwritten on the Error Count registers has occurred. = 1: indicate that one of the Error Count registers is overwritten. This bit is clear to 0 after the bit is read. Registers 04A-04FH, 0CA-0CFH, 14A-14FH, 1CA-1CFH, 24A-24FH, 2CA-2CFH, 34A-34FH, 3CA-3CFH: The PMON Error Count registers for a single framer are updated as a group by writing to any of the PMON count registers or updated every 1 second when the AUTOUPDATE (b0, T1/J1-000H) is set. The PMON Error Count registers for eight framers are updated by writing to the Chip ID/ Global PMON Update register (T1/J1-00CH). When the chip is reset, the contents of the PMON Error Count registers are unknown until the first latching of performance data is performed.
239
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 PMON BEE Count (LSB) (04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH) Bit No. Bit Name Type Default 7 BEE7 R X 6 BEE6 R X 5 BEE5 R X 4 BEE4 R X 3 BEE3 R X 2 BEE2 R X 1 BEE1 R X 0 BEE0 R X
T1 / J1 PMON BEE Count (MSB) (04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 BEE11 R X 2 BEE10 R X 1 BEE9 R X 0 BEE8 R X
In the ESF format, the BEE[11:0] represent the number of the CRC-6 errors, that is, the differences between the received CRC-6 and the local calculated CRC-6 In the SF format, the BEE[11:0] represent the number of the bit errors in the Frame Alignment Pattern. This register is updated on the defined intervals. T1 / J1 PMON FER Count (LSB) (04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH) Bit No. Bit Name Type Default 7 FER7 R X 6 FER6 R X 5 FER5 R X 4 FER4 R X 3 FER3 R X 2 FER2 R X 1 FER1 R X 0 FER0 R X
T1 / J1 PMON FER Count (MSB) (04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 FER8 R X
The FER[8:0] represent the number of the bit errors in the Frame Alignment Pattern. This register is updated on the defined intervals.
240
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 PMON OOF Count (04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH) Bit No. Bit Name Type Default 7 6 Reserved 5 4 OOF4 R X 3 OOF3 R X 2 OOF2 R X 1 OOF1 R X 0 OOF0 R X
The OOF[4:0] represent the number of the out of SF/ESF sync events and update on the defined intervals T1 / J1 PMON COFA Count (04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH) Bit No. Bit Name Type Default 7 6 5 Reserved 4 3 2 COFA2 R X 1 COFA1 R X 0 COFA0 R X
The COFA[2:0] represent the number of the changes of the Frame Alignment Pattern position and update on the defined intervals T1 / J1 RPLC Configuration (050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H) Bit No. Bit Name Type Default 7 6 5 4 Reserved 3 2 1 0 PCCE R/W 0
PCCE: = 0: the per-channel functions in RPLC are disabled. = 1: the per-channel functions in RPLC are enabled.
241
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RPLC P Access Status (051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H) Bit No. Bit Name Type Default 7 BUSY R 0 6 5 4 3 Reserved 2 1 0
BUSY: = 0: no reading or writing operation on the indirect registers. = 1: an internal indirect register is being accessed, any new operation on the internal indirect register is not allowed. This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 640ns. No more operations to the indirect registers could be done until this bit is cleared. T1 / J1 RPLC Channel Indirect Address / Control (052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H) Bit No. Bit Name Type Default 7 R/WB R/W 0 6 A6 R/W 0 5 A5 R/W 0 4 A4 R/W 0 3 A3 R/W 0 2 A2 R/W 0 1 A1 R/W 0 0 A0 R/W 0
Writing to this register with a valid address and R/WB bit initiates an internal operation cycle to the indirect registers. R/WB: = 0: write the data to the specified indirect register. = 1: read the data from the specified indirect register. A[6:0]: Specify the address of the indirect registers (from 01H to 48H) for the microprocessor access. T1 / J1 RPLC Channel Indirect Data Buffer (053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H) Bit No. Bit Name Type Default 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
This register holds the value which will be read from or written to the indirect registers (from 01H to 48H). If data are to be written to the indirect registers, the byte to be written must be written into this register before the target indirect register's address and R/WB=0 is written into the Address/ Control register, initiating the access. If data are to be read from the indirect registers, only the target indirect register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte. RPLC Indirect Registers Map Per-Channel Configuration for Channel 1 ~ 24 Data Trunk Conditioning Code for Channel 1 ~ 24 Signaling Trunk Conditioning for Channel 1 ~ 24
01H ~ 18H 19H ~ 30H 31H ~ 48H
242
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RPLC Per-Channel Configuration Registers (RPLC Indirect Registers 01H - 18H) Bit No. Bit Name Type Default 7 INVERT R/W X 6 DTRKC R/W X 5 DMW R/W X 4 SIGNINV R/W X 3 TEST R/W X 2 EXTRACT R/W X 1 FIX R/W X 0 POL R/W X
INVERT: This bit, together with the SIGNINV (b4, T1/J1-RPLC-indirect register - 01~18H), determines the bit inversion of the corresponding channel when output from the RSDn/MRSD pin. INVERT SIGNINV Bit Inversion 0 0 No bit inversion 0 1 Invert the MSB of the corresponding channel 1 0 Invert all the bits of the corresponding channel 1 1 Invert all the bits except the MSB of the corresponding channel DTRKC: = 0: disable the data in the corresponding channel to be replaced by the data set in the DTRK[7:0] (b7~0, T1/J1-19~30H) when output on the RSDn/MRSD pin. = 1: enable the data in the corresponding channel to be replaced by the data set in the DTRK[7:0] (b7~0, T1/J1-19~30H) when output on the RSDn/MRSD pin. DMW: = 0: disable the data in the corresponding channel to be replaced with a digital milliwatt pattern when output on the RSDn/MRSD pin. = 1: enable the data in the corresponding channel to be replaced with a digital milliwatt pattern when output on the RSDn/MRSD pin. SIGNINV: Refer to the INVERT (b7, T1/J1-RPLC-indirect register - 01~18H) TEST: = 0: disable the data in the corresponding channel to be tested by PRGD. = 1: enable the data in the corresponding channel to be extracted to PRGD for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 0), or enable the test pattern from PRGD to replace the data in the corresponding channel for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 1). All the channels that are extracted to the PRGD are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all channels set to be replaced with PRGD test pattern data are concatenated replaced by the PRBS. EXTRACT: This bit is valid in Receive Clock Slave Fractional T1/J1 mode: = 0: RSCKn is held in its inactivated state. = 1: RSCKn is clocked for the corresponding channel. FIX: = 0: disable the signaling bit of the corresponding channel to be fixed with the value set by the POL when output on the RSDn/MRSD pin. = 1: enable the signaling bit of the corresponding channel to be fixed with the value set by the POL when output on the RSDn/MRSD pin. POL: Valid when the FIX is logic 1: = 0: fix the signaling bit of the corresponding channel to be logic 0. = 1: fix the signaling bit of the corresponding channel to be logic 1. The priority of the RPLC operation of the corresponding channel on the RSDn/MRSD pin from high to low is: Extract data to PRGD for test; Replace the data with the value in the DTRK[7:0]; Replace the data with the milliwatt pattern; Replace the data with the pattern generated in the PRGD; Invert the bits in the channel; Fix the signaling bit.
243
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RPLC Data Trunk Conditioning Code Byte Registers (RPLC Indirect Registers 19H - 30H) Bit No. Bit Name Type Default 7 DTRK7 R/W X 6 DTRK6 R/W X 5 DTRK5 R/W X 4 DTRK4 R/W X 3 DTRK3 R/W X 2 DTRK2 R/W X 1 DTRK1 R/W X 0 DTRK0 R/W X
These indirect registers contain the data that will replace the data output on the RSDn/MRSD pin when the corresponding DTRKC (b6, T1/J1RPLC-indirect registers-01~18H) is logic 1. DTRK7 is the MSB. T1 / J1 RPLC Signaling Trunk Conditioning Byte Registers (RPLC Indirect Registers 31H - 48H) Bit No. Bit Name Type Default 7 STRKC R/W X 6 5 Reserved 4 3 A R/W X 2 B R/W X 1 C R/W X 0 D R/W X
STRKC: = 0: disable the signaling of the corresponding channel to be replaced by the data set in the A, B, C, D (b3~0, T1/J1-RPLC-indirect registers31~48H) when output on the RSSIGn/MRSSIG pin. = 1: enable the signaling of the corresponding channel to be replaced by the data set in the A, B, C, D (b3~0, T1/J1-RPLC-indirect registers31~48H) when output on the RSSIGn/MRSSIG pin. A, B, C, D: These bits contain the data that will replace the data output on the RSSIGn/MRSSIG pin when the corresponding STRKC (b7, T1/J1-RPLCindirect registers-31~48H) is logic 1. They are in the least significant nibble.
244
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RHDLC #1, #2 Configuration (054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 MEN R/W 0 2 MM R/W 0 1 TR R/W 0 0 EN R/W 0
Selection of the RHDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, T1/ J1-00DH). MEN, MM: The MEN & MM define the address matching mode: MEN MM Address Matching Mode 0 X No address matching is needed. All the HDLC data are stored in the FIFO. 1 0 The HDLC data are stored in the FIFO when the first byte is all ones or the same as the setting in the PA[7:0] (b7~0, T1/J1058H) or the SA[7:0] (b7~0, T1/J1-059H). 1 1 The HDLC data are stored in the FIFO when the most significant 6 bits in the first byte are all ones or the same as the setting in the PA[7:2] (b7~2, T1/J1-058H) or the SA[7:2] (b7~2, T1/J1-059H). TR: = 0: Normal operation. = 1: forces the RHDLC to immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts and initiate a new HDLC searching. This bit is clear to 0 after a rising and falling edge occur on the internal clock or after the register is read. EN: = 0: disabled the operation of the RHDLC block and all the FIFO buffer and interrupts are cleared. = 1: enabled the operation of the RHDLC block and the HDLC opening flag will be searched immediately. If the EN is set from logic 1 to logic 0 and back to logic 1, the RHDLC will immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts and initiate a new HDLC searching.
245
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RHDLC #1, #2 Interrupt Control (055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H) Bit No. Bit Name Type Default 7 INTE R/W 0 6 INTC[6] R/W 0 5 INTC[5] R/W 0 4 INTC[4] R/W 0 3 INTC[3] R/W 0 2 INTC[2] R/W 0 1 INTC[1] R/W 0 0 INTC[0] R/W 0
Selection of the RHDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, T1/ J1-00DH). INTE: = 0: disable the interrupt on the INT pin when there is a transition from 0 to 1 on the INTR (b0, T1/J1-056H). = 1: enable the interrupt on the INT pin when there is a transition from 0 to 1 on the INTR (b0, T1/J1-056H). INTC[6:0]: These bits set the interrupt set point of the FIFO buffer. Exceeding the set point will cause an interrupt, and the interrupt will persist until the FIFO is empty. The set point is decimal 128 when the INTC[6:0] is all zeros. The contents of this register should only be changed when the EN (b0, T1/J1-054H) is logic 0. This prevents any erroneous interrupt generation.
246
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RHDLC #1, #2 Status (056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H) Bit No. Bit Name Type Default 7 FE R X 6 OVR R X 5 COLS R X 4 PKIN R X 3 PBS[2] R X 2 PBS[1] R X 1 PBS[0] R X 0 INTR R X
Selection of the RHDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, T1/ J1-00DH). FE: = 0: the FIFO is loaded with data. = 1: the FIFO is empty. OVR: The overwritten condition occurs when data are written over unread data in the FIFO buffer. This bit is cleared to 0 after the register is read. = 0: no overwritten occurs. = 1: the FIFO is overwritten, and then the FIFO is reset , which cause the COLS and PKIN to be reset to logic 0. COLS: This bit reflects the HDLC link status change. = 0: normal operation. = 1: the first HDLC opening flag sequence (7E) activated the HDLC or the HDLC abort sequence (7F) deactivated the HDLC is detected. This bit is cleared to 0 after the bit is read, or after the OVR transitions to logic 1, or after the EN is cleared. PKIN: = 0: the last byte of a non-aborted packet is not written into the FIFO. = 1: the last byte of a non-aborted packet is written into the FIFO. This bit is cleared to 0 after the bit is read, or after the OVR transitions to logic 1. PBS[2:0]: The PBS[2:0] indicate the status of the last byte read from the FIFO. PBS[2:0] Status of the Data 000 Normal data 001 A dummy byte to indicate the first HDLC opening flag sequence (7E) was detected, which means the HDLC link became active. 010 A dummy byte to indicate the HDLC abort sequence (7F) was detected, which means the HDLC link became inactive. 011 Reserved 100 The last byte of a non-aborted HDLC packet was received. The HDLC packet is in an integer number of bytes and has no FCS error. 101 The last byte of a non-aborted HDLC packet was received and a non-integer number of bytes is in the packet. 110 The last byte of a non-aborted HDLC packet was received. The HDLC packet is in an integer number of bytes and has FCS error. 111 The last byte of a non-aborted HDLC packet was received. The HDLC packet is in a non-integer number of bytes and has FCS error. INTR: = 0: no interrupt sources in the HDLC Receiver block occurred. = 1: any one of the interrupt sources in the HDLC Receiver block occurred. The interrupt sources in the HDLC Receiver are: 1. Receiving the first 7E opening flag sequence which activates the HDLC link; 2. A packet was received; 3. Change of link status; 4. Exceeding the set point of the FIFO which is defined in the INTC[6:0] (b6~0, T1/J1-055H); 5. Over-writting the FIFO. This bit is cleared to 0 after the bit is read.
247
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RHDLC #1, #2 Data (057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H) Bit No. Bit Name Type Default 7 RD[7] R X 6 RD[6] R X 5 RD[5] R X 4 RD[4] R X 3 RD[3] R X 2 RD[2] R X 1 RD[1] R X 0 RD[0] R X
Selection of the RHDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, T1/ J1-00DH). RD[7:0]: These bits represent the bytes read from the FIFO. These bits should not be accessed at a rate greater than 1/15 of the XCK rate. The RD[0] corresponds to the first bit of the serial received data from the FIFO. T1 / J1 RHDLC #1, #2 Primary Address Match (058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H) Bit No. Bit Name Type Default 7 PA[7] R/W 1 6 PA[6] R/W 1 5 PA[5] R/W 1 4 PA[4] R/W 1 3 PA[3] R/W 1 2 PA[2] R/W 1 1 PA[1] R/W 1 0 PA[0] R/W 1
Selection of the RHDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, T1/ J1-00DH). PA[7:0]: These bits stipulate the primary address pattern. PA[0] compares to the first bit of the serial data. T1 / J1 RHDLC #1, #2 Second Address Match (059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H) Bit No. Bit Name Type Default 7 SA[7] R/W 1 6 SA[6] R/W 1 5 SA[5] R/W 1 4 SA[4] R/W 1 3 SA[3] R/W 1 2 SA[2] R/W 1 1 SA[1] R/W 1 0 SA[0] R/W 1
Selection of the RHDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, T1/ J1-00DH). SA[7:0]: These bits stipulate the secondary address pattern. SA[0] compares to the first bit of the serial data.
248
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 TBOM Code (05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH) Bit No. Bit Name Type Default 7 Reserved 6 5 BOC[5] R/W 1 4 BOC[4] R/W 1 3 BOC[3] R/W 1 2 BOC[2] R/W 1 1 BOC[1] R/W 1 0 BOC[0] R/W 1
When the BOC[5:0] are written with any 6-bit code other than the `111111', the code will be transmitted as the Bit Oriented Message (BOM), overwriting any HDLC packets currently being transmitted. The BOM pattern is `111111110BOC[0]BOC[1]BOC[2]BOC[3]BOC[4]BOC[5]0', that is, the BOC[0] is transmitted first.
249
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 PRGD Control (060H) Bit No. Bit Name Type Default 7 PDR[1] R/W 0 6 PDR[0] R/W 0 5 Reserved 4 PS R/W 0 3 TINV R/W 0 2 RINV R/W 0 1 AUTOSYNC R/W 1 0 MANSYNC R/W 0
PDR[1:0]: The PDR[1:0] define the function of the four PRGD Pattern Detector registers: PDR[1:0] PRGD Pattern Detector Registers (#1 ~ #4) 00, 01 Pattern Receive 10 Error Count 11 Bit Count (The #1 is the LSB, while the #4 is the MSB.) PS: = 0: a pseudo-random pattern is generated/detected by the PRGD. = 1: a repetitive pattern is generated/detected by the PRGD. This bit should be set first of all the PRGD registers. TINV: = 0: disable inverting the generated pattern before being transmitted. = 1: enable inverting the generated pattern before being transmitted. RINV: = 0: disable inverting the received pattern before being processed. = 1: enable inverting the received pattern before being processed. AUTOSYNC: = 0: disable automatic re-search for the sync of the pattern after the pattern is out of synchronization. = 1: enable automatic re-search for the sync of the pattern after the pattern is out of synchronization. MANSYNC: Trigger on the rising edge. A transition from logic 0 to logic 1 on this bit manually initiates a re-search for the sync of a pattern. Each time the value of the PRGD registers is changed or the detector data source changes, a manual sync operation is recommended to ensure that the detector works correctly.
250
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 PRGD Interrupt Enable / Status (061H) Bit No. Bit Name Type Default 7 SYNCE R/W 0 6 BEE R/W 0 5 XFERE R/W 0 4 SYNCV R X 3 SYNCI R X 2 BEI R X 1 XFERI R X 0 OVR R X
SYNCE: = 0: disable the interrupt on the INT pin when the SYNCI is logic one. = 1: enable the interrupt on the INT pin when the SYNCI is logic one. BEE: = 0: disable the interrupt on the INT pin when at least one bit error has been detected in the received pattern. = 1: enable the interrupt on the INT pin when at least one bit error has been detected in the received pattern. XFERE: = 0: disable the interrupt on the INT pin when the the data in the PRGD pattern detector register is updated. = 1: enable the interrupt on the INT pin when the the data in the PRGD pattern detector register is updated. SYNCV: = 0: the pattern is out of sync (the pattern detector has detected 10 or more bit errors in a fixed 48-bit window). = 1: the pattern is in sync (the pattern detector has observed at least 48 consecutive error-free bit periods). SYNCI: = 0: there is no transition on the SYNCV. = 1: there is a transition (from 0 to 1 or from 1 to 0) on the SYNCV. This bit is cleared to 0 after the bit is read. BEI: = 0: no bit error is detected in the received pattern. = 1: at least one bit error has been detected in the received pattern. This bit is cleared to 0 after the bit is read. XFERI: = 0: the data in the PRGD pattern detector register is not updated. = 1: the data in the PRGD pattern detector register is updated. This bit is cleared to 0 after the bit is read. OVR: = 0: the PRGD pattern detector register is not overwritten. = 1: the PRGD pattern detector register is overwritten. This bit is cleared to 0 after the bit is read.
251
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 PRGD Shift Register Length (062H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 PL[4] R/W 0 3 PL[3] 2 PL[2] 1 PL[1] 0 PL[0]
R/ W
0
R/ W
0
R/ W
0
R/ W
0
These bits determine the length of the valid data in the PRGD pattern insertion register. The length is equal to the value of PL[4:0] + 1. T1 / J1 PRGD Tap (063H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 PT[4] R/W 0 3 PT[3] R/W 0 2 PT[2] R/W 0 1 PT[1] R/W 0 0 PT[0] R/W 0
These bits determine the feedback tap position of the generated pseudo random pattern before it is transmitted. The feedback tap position is equal to the value of PT[4:0] + 1. In application, the PT is always less than the PL. T1 / J1 PRGD Error Insertion (064H) Bit No. Bit Name Type Default 7 6 Reserved 5 4 3 EVENT R/W 0 2 EIR[2] R/W 0 1 EIR[1] R/W 0 0 EIR[0] R/W 0
EVENT: A single bit error is generated when the state of this bit is changed from 0 to 1. To insert another bit error, this bit must be cleared to 0, and then set from 0 to 1 again. EIR[2:0]: The EIR[2:0] bits determine the bit error rate that will be inserted in the PRGD test pattern. If the bit error rate is changed from one non- zero value to another non-zero value, it is recommended to set the EIR[2:0] to `000' first, then set the EIR[2:0] to the desired value. EIR[2:0] Bit error rate 000 No error inserted 001 No error inserted 010 10-2 011 10-3 100 10-4 101 10-5 110 10-6 111 10-7
252
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
T1 / J1 PRGD Pattern Insertion #1 (068H) Bit No. Bit Name Type Default 7 PI[7] R/W 0 6 PI[6] R/W 0 5 PI[5] R/W 0 4 PI[4] R/W 0 3 PI[3] R/W 0 2 PI[2] R/W 0 1 PI[1] R/W 0 0 PI[0] R/W 0
T1 / J1 PRGD Pattern Insertion #2 (069H) Bit No. Bit Name Type Default 7 PI[15] R/W 0 6 PI[14] R/W 0 5 PI[13] R/W 0 4 PI[12] R/W 0 3 PI[11] R/W 0 2 PI[10] R/W 0 1 PI[9] R/W 0 0 PI[8] R/W 0
T1 / J1 PRGD Pattern Insertion #3 (06AH) Bit No. Bit Name Type Default 7 PI[23] R/W 0 6 PI[22] R/W 0 5 PI[21] R/W 0 4 PI[20] R/W 0 3 PI[19] R/W 0 2 PI[18] R/W 0 1 PI[17] R/W 0 0 PI[16] R/W 0
T1 / J1 PRGD Pattern Insertion #4 (06BH) Bit No. Bit Name Type Default 7 PI[31] R/W 0 6 PI[30] R/W 0 5 PI[29] R/W 0 4 PI[28] R/W 0 3 PI[27] R/W 0 2 PI[26] R/W 0 1 PI[25] R/W 0 0 PI[24] R/W 0
When a repetitive pattern is selected to transmit, the data in these registers are the repetitive pattern. When a pseudo random pattern is selected to transmit, the data in these registers should be set to FFFFFFFFH. They are the initial value for the pseudo random pattern. Writing to PI[31:24] updates the PRGD configuration. When a repetitive pattern is transmitted, the PI[31] is transmitted first, followed by the remaining bits in sequence down to PI[0]. The length of the valid data in these four registers is determined by the PL[4:0]. When the length is less than 31, the bits in higher PI are not used.
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T1 / J1 PRGD Pattern Detector #1 (06CH) Bit No. Bit Name Type Default 7 PD[7] R X 6 PD[6] R X 5 PD[5] R X 4 PD[4] R X 3 PD[3] R X 2 PD[2] R X 1 PD[1] R X 0 PD[0] R X
T1 / J1 PRGD Pattern Detector #2 (06DH) Bit No. Bit Name Type Default 7 PD[15] R X 6 PD[14] R X 5 PD[13] R X 4 PD[12] R X 3 PD[11] R X 2 PD[10] R X 1 PD[9] R X 0 PD[8] R X
T1 / J1 PRGD Pattern Detector #3 (06EH) Bit No. Bit Name Type Default 7 PD[23] R X 6 PD[22] R X 5 PD[21] R X 4 PD[20] R X 3 PD[19] R X 2 PD[18] R X 1 PD[17] R X 0 PD[16] R X
T1 / J1 PRGD Pattern Detector #4 (06FH) Bit No. Bit Name Type Default 7 PD[31] R X 6 PD[30] R X 5 PD[29] R X 4 PD[28] R X 3 PD[27] R X 2 PD[26] R X 1 PD[25] R X 0 PD[24] R X
When the PDR[1:0] (b7~6, T1/J1-060H) are set to 00 or 01, the four PRGD pattern detector registers are configured as Pattern Receive registers. They reflect the content of the received pattern. When the PDR[1:0] (b7~6, T1/J1-060H) are set to 10, the four PRGD pattern detector registers are configured as Error Counter registers. The value in these registers represent the number of bit errors. The bit errors are not accumulated when the pattern is out of sync. When the PDR[1:0] (b7~6, T1/J1-060H) are set to 11, the four PRGD pattern detector registers are configured as Bit Counter registers. The value in these registers represent the total received bit number. These registers are updated each second automatically, or by writing to any of these four registers, or to the Revision / Chip ID / Global PMON register.
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INDUSTRIAL TEMPERATURE RANGES
T1 / J1 RHDLC Receive Data Link 2 Control (TXCISEL = 0) (070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H) Bit No. Bit Name Type Default 7 DL2_EVEN R/W 0 6 DL2_ODD R/W 0 5 Reserved 4 DL2_TS[4] R/W 0 3 DL2_TS[3] R/W 0 2 DL2_TS[2] R/W 0 1 DL2_TS[1] R/W 0 0 DL2_TS[0] R/W 0
When the TXCISEL (b3, T1/J1-00DH) is 0, this register is used for the Receive HDLC #2. DL2_EVEN: = 0: the data is not extracted from the even frames. = 1: the data is extracted from the even frames. DL2_ODD: = 0: the data is not extracted from the odd frames. = 1: the data is extracted from the odd frames. DL2_TS[4:0]: These bits binary define one channel of even and/or odd frames to extract the data from. They are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. T1 / J1 RHDLC Data Link 2 Bit Select (TXCISEL = 0) (071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H) Bit No. Bit Name Type Default 7 DL2_BIT[7] R/W 0 6 DL2_BIT[6] R/W 0 5 DL2_BIT[5] R/W 0 4 DL2_BIT[4] R/W 0 3 DL2_BIT[3] R/W 0 2 DL2_BIT[2] R/W 0 1 DL2_BIT[1] R/W 0 0 DL2_BIT[0] R/W 0
When the TXCISEL (b3, T1/J1-00DH) is 0, this register is used for the Receive HDLC #2. DL2_BITn: = 0: the data is not extracted from the corresponding bit. = 1: the data is extracted from the corresponding bit of the assigned channel. These bits are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. The DL1_BIT[7] corresponds to the first bit (MSB) of the selected channel.
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T1 / J1 THDLC Transmit Data Link 2 Control (TXCISEL = 1) (070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H) Bit No. Bit Name Type Default 7 DL2_EVEN R/W 0 6 DL2_ODD R/W 0 5 Reserved 4 DL2_TS[4] R/W 0 3 DL2_TS[3] R/W 0 2 DL2_TS[2] R/W 0 1 DL2_TS[1] R/W 0 0 DL2_TS[0] R/W 0
When the TXCISEL (b3, T1/J1-00DH) is 1, this register is used for the Transmit HDLC #2. DL2_EVEN: = 0: the data is not inserted to the even frames. = 1: the data is inserted to the even frames. DL2_ODD: = 0: the data is not inserted to the odd frames. = 1: the data is inserted to the odd frames. DL2_TS[4:0]: These bits binary define one channel of even and/or odd frames to insert the data to. They are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. T1 / J1 THDLC Data Link 2 Bit Select (TXCISEL = 1) (071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H) Bit No. Bit Name Type Default 7 DL2_BIT[7] R/W 0 6 DL2_BIT[6] R/W 0 5 DL2_BIT[5] R/W 0 4 DL2_BIT[4] R/W 0 3 DL2_BIT[3] R/W 0 2 DL2_BIT[2] R/W 0 1 DL2_BIT[1] R/W 0 0 DL2_BIT[0] R/W 0
When the TXCISEL (b3, T1/J1-00DH) is 1, this register is used for the Transmit HDLC #2. DL2_BITn: = 0: the data is not inserted to the corresponding bit. = 1: the data is inserted to the corresponding bit of the assigned channel. These bits are invalid when the DL2_EVEN and the DL2_ODD are both logic 0. The DL1_BIT[0] corresponds to the first bit (MSB) of the selected channel.
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T1 / J1 RESI Timeslot Offset (077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H) Bit No. Bit Name Type Default 7 Reserved 6 TSOFF[6] R/W 0 5 TSOFF[5] R/W 0 4 TSOFF[4] R/W 0 3 TSOFF[3] R/W 0 2 TSOFF[2] R/W 0 1 TSOFF[1] R/W 0 0 TSOFF[0] R/W 0
In the Receive Clock Slave mode, when the data rate on the system side is 2.048M bit/s (the RSCCK2M [b4, T1/J1-001H] and RSCCK8M [b3, T1/J1-001H] are set to `10'), these bits determine the channel offset between the RSCFS and the start of the corresponding frame on the RSDn (and RSSIGn). In the Receive Multiplexed mode, these bits determine the channel offset between the MRSCFS and the start of the corresponding frame on the MRSD and MRSSIG. In the Receive Clock Slave mode, when the data rate on the system side is 1.544M bit/s, and in Receive Clock Master mode, the channel offset is disabled. Thus, the TSOFF must be set to 0. They define a binary number. The offset can be set from 0 to 127 channels.
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T1 / J1 RESI Timeslot Offset (078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H) Bit No. Bit Name Type Default 7 Reserved 6 FPINV R/W 0 5 RSD_RSCFS_EDGE R/W 0 4 CMS R/W 0 3 BOFF_EN R/W 0 2 BOFF[2] R/W 0 1 BOFF[1] R/W 0 0 BOFF[0] R/W 0
FPINV: = 0: The receive framing pulse RSCFS and RSFSn/MRSFS are active high. = 1: The receive framing pulse RSCFS and RSFSn/MRSFS are active low. When the bit indicates the RSCFS and MRSFS polarity, the bits of all eight framers must have the same value. RSD_RSCFS_EDGE: Valid when the CMS (b4, T1/J1-078H) is logic 1 and the setting in the RSCFSFALL (b1, T1/J1-003H) and that in the RSCCKRISE (b0, T1/J1003H) are equal. = 0: select the second active edge of the RSCCK to update the signal on the RSDn, RSSIGn and RSFSn pins, or select the first active edge of the MRSCCK to update the signal on the MRSD, MRSSIG and MRSFS pins. = 1: select the first active edge of the RSCCK to update the signal on the RSDn, RSSIGn and RSFSn pins, or select the second active edge of the MRSCCK to update the signal on the MRSD, MRSSIG and MRSFS pins. (The signal on the RSCFS/MRSCFS pin is always sampled on the first active edge.) In Receive Multiplexed mode, the RSD_RSCFS_EDGE in all eight framers should be set to the same value. CMS: = 0: the bit rate of RSCCK/MRSCCK is the same as the bit rate of the backplane. = 1: the bit rate of RSCCK/MRSCCK is twice the bit rate of the backplane. The CMS in all eight framers should be set to the same value. BOFF_EN: Valid when the CMS (b4, T1/J1-078H) is 0. = 0: disable the bit offset. = 1: enable the bit offset. BOFF[2:0]: Valid when the CMS (b4, T1/J1-078H)is 0 and the BOFF_EN is logic 1. In Receive Clock Slave mode, when the data rate in the system side is 2.048M bit/s (the RSCCK2M [b4, T1/J1-001H] and RSCCK8M [b3, T1/J1001H] are set to `10'), these bits determine the bit offset between the RSCFS and the start of the corresponding frame on the RSDn (and RSSIGn). In Receive Multiplexed mode, these bits determine the bit offset between the MRSCFS and the start of the corresponding frame on the MRSD and MRSSIG. In Receive Clock Slave mode, when the data rate in the system side is 1.544M bit/s, and in Receive Clock Master mode, the bit offset is disabled. These bits define a binary number. Programming of the Bit Offsets is consistent with the convention established by the Concentration Highway Interface (CHI) specification. Refer to the Functional Description for details.
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6 IEEE STD 1149.1 JTAG TEST ACCESS PORT
The IDT82V2108 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) controller. Control of the TAP is achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data are shifted into the registers via the Test Data Input (TDI) pin, and shifted out of the registers via the Test Data Output (TDO) pin. Both TDI and TDO are clocked at a rate determined by TCK. The JTAG boundary scan registers includes BSR (Boundary Scan Register), IDR (Device Identification Register), BR (Bypass Register) and IR (Instruction Register). These will be described in the following pages. Refer to Figure - 83 for architecture.
BSR (Boundary Scan Register)
IDR (Device Identification Register) TDI BR (Bypass Register)
MUX
MUX
TDO
IR (Instruction Register)
Control<6:0> TMS TRST TCK TAP (Test Access Port) Controller Select Output Enable
Figure - 83. JTAG Architecture
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Table - 64. IR Code IR CODE 000 INSTRUCTION EXTEST COMMENTS The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. The SAMPLE/PRELOAD instruction is used to allow scanning of the boundary-scan register without causing interference to the normal operation of the on-chip system logic. Data received at system input pins is supplied without modification to the on-chip system logic; data from the on-chip system logic is driven without modification through the system output pins. SAMPLE allows a snapshot to be taken of the data flowing from the system pins to the on-chip system logic or vice versa, without interfering with the normal operation of the assembled board. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of boundary-scan register cells prior to selection of another boundary-scan test operation. The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. The BYPASS instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device. This instruction allows the state of the signals driven from device pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between TDI and TDO. The signals driven from the device pins will not change while the CLAMP instruction is selected. Use of the HIGHZ instruction places the device in a state in which all of its system logic outputs are placed in an inactive drive state (e.g., high impedance). In this state, and in-circuit test system may drive signals onto the connections normally driven by a device output without incurring the risk of damage to the device. (for manufactory test)
010
SAMPLE / PRELOAD
001 111 100
IDCODE BYPASS CLAMP
101
HIGHZ
011
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6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR)
The IR (Instruction Register) with instruction decode block is used to select the test to be executed or the data register to be accessed or both. The instructions are shifted in LSB first to this 3-bit register. See Table - 64 for details of the codes and the instructions related.
6.2.2 BYPASS REGISTER (BYR) The BYR consists of a single bit. It can provide a serial path between the TDI input and TDO output, bypassing the BYR to reduce test access times. 6.2.3 BOUNDARY SCAN REGISTER (BSR) The scan chain uses 3 types of cells: * Input / Output cells: When used as input, the cells are able to sample and control the state of an external signal during BS tests. When used as output, the cells are able to control the state of an external signal during BS tests. * In/Out or Tri-state output cells: When configured as input, the cells are able to sample and control the state of an external signal. When configured as output, the cells are able to control the state of an external signal. * Control cell: This cell provides a signal for direction control of bidirectional or tri-state output pins during BS tests. The Boundary Scan sequence and the I/O Pad Cell type are illustrated in Table - 66:
6.2
JTAG DATA REGISTER
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) The IDR can be set to define the Vision, the Part Number, the Manufacturer Identity and a fixed bit. The IDR is 32 bits long and is partitioned as in Table - 65. Data from the IDR is shifted out to the TDO LSB first. Table - 65. IDR BIT No. 0 1~11 12~27 28~31 COMMENTS Set to "1" Manufacturer Identity (033H) Part Number (04D0H) Version (2H)
6.3
TEST ACCESS PORT CONTROLLER
The TAP controller is a 16-state synchronous state machine. Figure 84 shows its state diagram. A description of each state follows. Note that the figure contains two main branches to access either the data or instruction registers. The value shown next to each state transition in this figure states the value present at TMS at each rising edge of TCK. Please refer to Table - 67 for details of the state description.
Table - 66. Boundary Scan Sequence and the I/O Pad Cell Type Pin_name LRD[1] LRCK[1] LRD[2] LRCK[2] LRD[3] LRCK[3] LRD[4] LRCK[4] LTD[1] LTCK[1] LTD[2] LTCK[2] LTD[3] LTCK[3] LTD[4] LTCK[4] LTD[5] LTCK[5] LTD[6] LTCK[6] LTD[7] Cell Type Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output BS * 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108
261
Pin_name LTCK[7] LTD[8] LTCK[8] LRD[5] LRCK[5] LRD[6] LRCK[6] LRD[7] LRCK[7] LRD[8] LRCK[8] RST INT D[7:0]_EN D[0] D[1] D[2] D[3] D[4] D[5] D[6]
Cell Type Output Output Output Input Input Input Input Input Input Input Input Input Output Control In/Out In/Out In/Out In/Out In/Out In/Out In/Out
BS * 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87
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Pin_name D[7] ALE A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] CS WR RD RSFS[8] RSCK[8]/RSSIG[8] RSCK[8]/RSSIG[8]_EN RSD[8] RSD[8]_EN RSFS[7] RSCK[7]/RSSIG[7] RSCK[7]/RSSIG[7]_EN RSD[7] RSD[7]_EN RSFS[6] RSCK[6]/RSSIG[6] RSCK[6]/RSSIG[6]_EN RSD[6] RSD[6]_EN RSFS[5] RSCK[5]/RSSIG[5] RSCK[5]/RSSIG[5]_EN RSD[5] RSD[5]_EN RSFS[4] RSCK[4]/RSSIG[4] RSCK[4]/RSSIG[4]_EN RSD[4] RSD[4]_EN RSFS[3] RSCK[3]/RSSIG[3] RSCK[3]/RSSIG[3]_EN RSD[3] RSD[3]_EN RSFS[2]/MRSFS[2] RSCK[2]/RSSIG[2]/MRSSIG[2] RSCK[2]/RSSIG[2]/MRSSIG[2]_EN
Cell Type In/Out Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Tri-state Output Control Tri-state Output Control Output Tri-state Output Control Tri-state Output Control Output Tri-state Output Control Tri-state Output Control Output Tri-state Output Control Tri-state Output Control Output Tri-state Output Control Tri-state Output Control Output Tri-state Output Control Tri-state Output Control Output Tri-state Output Control
BS * 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
Pin_name Cell Type RSD[2]/MRSD[2] Tri-state Output RSD[2]/MRSD[2]_EN Control RSFS[1]/MRSFS[1] Output RSCK[1]/RSSIG[1]/MRSSIG[1] Tri-state Output RSCK[1]/RSSIG[1]/MRSSIG[1]_EN Control RSD[1]/MRSD[1] Tri-state Output RSD[1]/MRSD[1]_EN Control TSSIG[8]/TSFS[8] In/Out TSSIG[8]/TSFS[8]_EN Control TSD[8] Input TSSIG[7]/TSFS[7] In/Out TSSIG[7]/TSFS[7]_EN Control TSD[7] Input TSSIG[6]/TSFS[6] In/Out TSSIG[6]/TSFS[6]_EN Control TSD[6] Input TSSIG[5]/TSFS[5] In/Out TSSIG[5]/TSFS[5]_EN Control TSD[5] Input TSSIG[4]/TSFS[4] In/Out TSSIG[4]/TSFS[4]_EN Control TSD[4] Input TSSIG[3]/TSFS[3] In/Out TSSIG[3]/TSFS[3]_EN Control TSD[3] Input TSFS[2]/TSSIG[2]/MTSSIG[2] In/Out TSFS[2]/TSSIG[2]/MTSSIG[2]_EN Control TSD[2]/MTSD[2] Input TSFS[1]/TSSIG[1]/MTSSIG[1] In/Out TSFS[1]/TSSIG[1]/MTSSIG[1]_EN Control TSD[1]/MTSD[1] Input XCK Input RSCFS/MRSCFS Input RSCCK/MRSCCK Input TSCFS/MTSCFS Input TSCCKB/MTSCCKB Input TSCCKA Input
Note: * BS means Boundary Scan Sequence
BS * 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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Table - 67. TAP Controller State Description
STATE Test Logic Reset Run-Test/Idle DESCRIPTION In this state, the test logic is disabled to continue normal operation of the device. During initialization, the device initializes the instruction register with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to the Select-DR state. This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan state. In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low. In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state. This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this state. In this controller state, the shift register contained in the instruction register loads a fixed value of `100' on the rising edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the Shift-IR state if TMS is held low.
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Capture-IR
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STATE Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
DESCRIPTION In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or remains in the Shift-IR state if TMS is held low. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain their previous value.
1
Test-logic Reset 0
0 Run Test/Idle
1
Select-DR 0 1 Capture-DR 0
1
Select-IR 0 1 Capture-IR 0
1
0 Shift-DR 1 Exit1-DR 0 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 1 Shift-IR 1 Exit1-IR 0
0
1
0
Figure - 84. JTAG State Diagram
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IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
7
7.1
PHYSICAL AND ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Min -65C -0.3V VDD-0.3V -0.3V 2000V 1000V 100ma Max +150C 4.6V 5.5V BIAS+0.3V 230C
Storage temperature Voltage on VDD w.r.t. GND Voltage on BIAS w.r.t. GND Voltage on any pin Maximum lead temperature ESD Performance (HBM) ESD Performance (CDM) Latch-up current on any pin Maximum DC current on any pin Maximum lead temperature Maximum junction temperature
during TBC seconds
7.2
OPERATING CONDITIONS
@ TA = -40 to +85 C, VDD = 3.3V 10%, VDDBIAS5.5V
7.3
D.C. CHARACTERISTICS
Description Core Power Supply 5V Tolerant Bias Current into 5V Bias Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage Input Low Current Input Low Current Input High Current Operating current Operating current Operating current Min 2.97 VDD 0 2.0 2.4 1.50 0.83 0.17 -70 -1 -10 Typ 3.3 5.0 1 Max 3.63 5.5 3 0.8 BIAS 0.4 2.0 1.33 1.17 -450 +1 +10 Unit V V mA V V V V V V V uA uA uA mA mA mA Test Conditions
Parameter VDDC, VDDIO BIAS IBIAS VIL VIH VOL VOH VT+ VTVTH IILPU IIL IIH IDDOP1 IDDOP2 IDDOP3
VBIAS=5.5V
VDD=min, IOL= 2mA, 3mA VDD=min, IOL= 3mA, 3mA
1.75 1.10 0.65 -330 0 0 160 170 120
VIL=GND VIL=GND VIH=VBIAS E1 mode, XCK=49.152MHz, TSCCKB=2.048MHz, output unloaded, Vdd=3.63V. E1 mode, XCK=49.152MHz, TSCCKB=8.192MHz, output unloaded. Vdd=3.63V. T1 mode, XCK=37.056MHz, TSCCKB=1.544MHz, output unloaded. Vdd=3.63V.
265
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
7.4
The RST must be asserted for a minimum of 100 ns after XCLK is stable to ensure that the chip is completely reset. CLOCK PARAMETERS E1 CONFIGURATION Min. Frequency (MHz) Max. Frequency (MHz) 49.152 2.0 8.0 2.0 2.0 2.0 2.1 8.4 2.1 2.1 2.1 ppm 50 TL min (ns) * 100 40 100 140 140 TH min (ns)* 100 40 100 140 140
CLOCK AND RESET TIMING
7.4.1
XCK LRCK MRSCCK TSCCKA RSCCK TSCCKB 7.4.2
CLOCK PARAMETERS T1/J1 CONFIGURATION Min. Frequency (MHz) Max. Frequency (MHz) 37.056 1.534 8.00 1.534 1.50 1.50 1.545 8.40 1.545 2.058 4 2.10 4 ppm 32 2 TL min 1 100 40 100 140 140 TH min 1 100 40 100 140 140
XCK LRCK MRSCCK TSCCKA RSCCK TSCCKB
3
NOTE: 1. The T L and T H are defined in the figure.
TH clock in the above two tables
TL
2. An XCK input accuracy of 100 ppm is only acceptable if an accurate line rate reference is provided. If TJAT is left to free-run without a reference, or referenced to a derivative of XCK, then XCK accuracy must be 32 ppm. The accuracy of XCK affect the performance of TJAT/RJAT. 3. An XCK input accuracy of 100 ppm is only acceptable if an accurate line rate reference is provided. If TJAT is left to free-run without a reference, or referenced to a derivative of XCLK, then XCLK accuracy must be 32 ppm. The accuracy of XCLK affect the performance of TJAT/DJAT. 4. For T1 mode with 2.048Mb/s back-plane data rate only.
266
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
7.5
MICROPROCESSOR READ ACCESS TIMING
Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tZRD tPRD tZINTH tVRD tW2R Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Time Latch to Read Hold Valid Read Negated to Output Tri-state Valid Read to Valid Data Propagation Delay Valid Read Negated to INT Inactive Valid Read Width Valid interval from last write to next read Min 0 0 5 5 10 0 0 E1 T1 E1 T1 E1 T1 E1 T1 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20 130 160 145 185 120 150 120 150
tSAR A[9:0] tSALR ALE tVL tVRD CS+RD INT tPRD D[7:0] CS+WR tSLR tZINTH Valid Address tHALR
tHAR
tZRD Vald Data
tW2R
Figure - 85. Read Access Timing
Notes: 1. Output propagation delay time is the time from the VDD/2 point of the reference signal to the 1.4V point of the output. 2. Maximum output propagation delays are measured with a 100pF load on the MPIF data bus D[7:0]. 3. All the set-up time or hold time are defined as the time between the VDD/2 point of the reference signal. 4. In non-multiplexed mode, ALE can be held high, tSALR, tHALR, tVL, tSLR and tH LR are not applicable. 5. Parameter tH AR is not applicable when address latching is used. The interval of read accesses should > = 180 ns.
267
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
7.6
MICROPROCESSOR WRITE ACCESS TIMING
Symbol tSAW tSDW tSALW tHALW tVL tHLW tHDW tHAW tW2W Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Write to write interval Min 5 0 5 5 5 5 5 5 80 100 MAX Units ns ns ns ns ns ns ns ns ns ns
E1 T1
A[9:0]
tSALW
Valid
tVL tSAW
Address
tHALW tHLW tHAW tW2W
ALE CS+WR
tSDW
tHDW
D[7:0]
Vald Data
Figure - 86. Write Access Timing
Notes: 1. Output propagation delay time is the time from the VDD/2 point of the reference signal to the VDD/2 point of the output. 2. All the set-up time or hold time are defined as the time between the VDD/2 point of the reference signal. 3. In non-multiplexed mode, ALE can be held high, tSALW, tHALW, tVL, tSLW and tH LW are not applicable. 4. Parameter tH AW and tSAW are not applicable when address latching is used.
268
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
7.7
7.7.1
I/O TIMING CHARACTERISTICS
TRANSMIT SYSTEM INTERFACE TIMING
Note that timing information can refer to the positive or negative edge of the reference clock. The active clock edge is selected by configuration flags. Symbol Tprop Ts Thold Parameter Propagation delay Set up time Hold time Min 0 15 10 Typ Max 20 Unit ns ns ns
TSCCKB
Tprop
TSFS[x]
Ts Thold
TSD[x] TSSIG[x] TSCFS
Figure - 87. Transmit Interface Timing (Transmit System Common Clock #B)
LTCK[x]
Tprop
TSFS[x]
Ts Thold
TSD[x]
Figure - 88. Transmit Interface Timing (Line Transmit Clock)
269
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
7.7.2
RECEIVE SYSTEM INTERFACE TIMING
Note that timing information can refer to the positive or negative edge of the reference clock. The active clock edge is selected by configuration flags. Symbol Tprop Ts Thold Parameter Propagation delay Set up time Hold time Min 0 10 10 Typ Max 20 Unit ns ns ns
RSCCK
Tprop
RSD[x] RSSIG[x] RSFS[x]
Ts Thold
RSCFP
Figure - 89. Receive Interface Timing (Receive System Common Clock)
RSCK[x]
Tprop
RSD[x] RSPS[x]
Figure - 90. Receive Interface Timing (Receive System Clock)
270
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
7.7.3
RECEIVE & TRANSMIT LINE TIMING
Note that timing information can refer to the positive or negative edge of the reference clock. The active clock edge is selected by configuration flags. 7.7.3.1 Receive Line Interface Timing Parameter Setup Time Hold Time Min 10 10 Typ Max Unit ns ns
Symbol Ts Th
LRCK[x]
Ts Thold
LRD[x]
Figure - 91. Receive Line Interface Timing
7.7.3.2
Transmit Line Interface Timing Parameter Propagation delay Min -10 Typ Max 10 Unit ns
Symbol Tprop
TLCLK[x]
Tprop
TLD[x]
Figure - 92. Transmit Line Interface Timing
271
IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXXXX Device Type XX Package X Process/Temperature Range BLANK BB PX 82V2108 Industrial (-40 C to +85 C) Plastic Ball Grid Array (PBGA, BB144) Plastic Quad Flat Pack (PQFP128) T1 / E1 / J1 Octal Framer
Data Sheet Document History
07/30/2002 pgs 48, 50, 199 09/09/2002 pgs 32, 33, 123, 125, 190, 236 01/15/2003 pgs 1, 272
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